Abstract: Circuits embodying the invention include apparatus for sensing the amplitude and the frequency of the signals received from one section of a telephone cable and for propagating onto the succeeding section of telephone cable only those received signals having an amplitude greater than a predetermined level and whose frequency is within the predetermined range.

Abstract: A current sensing circuit includes a first reference resistor connected in series with the source-drain path of a current mirroring transistor across the source-drain path of a power transistor which is N times the size of the current mirroring transistor. Due to the first reference resistor, the current in the mirroring transistor is less than l/N the current in the power transistor. To sense the current in the power transistor more accurately, the current sensing circuitry includes a reference circuit in which the source-drain path of a compensating transistor, of like size as the current mirroring transistor, is connected in parallel with a second reference resistor to produce a reference current which is approximately equal to l/N the current flowing in the power transistor.

Abstract: A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.

Abstract: A programmable logic gate array employing a plurality of reprogrammable fuses having a logical NAND characteristic for logically connecting selected inputs to selected logic gates. The fuses are selectively programmed for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.

Abstract: An impedance transforming circuit for multibit digital word signals includes plural transmission paths for respective signals of a word. At least some of the paths have different output impedances but present essentially the same signal propagation delay. Each path includes plural, tandem connected, transistor switches; and each switch comprises, with correspondingly located switches of other paths, a stage of the transforming circuit. Output conductances of the switches of a path are scaled along the path according to a stage-to-stage ration F selected to minimize the number of stages required to achieve a desired signal propagation time through the path. At any stage switch where the ratio F cannot be directly accommodated, the selected value of F is achieved by dividing the stage output conductance between an in-path switch, that satisfies that ratio F with respect to a driven stage and a dummy-load switch that, together with the in-path switch, satisfies the ratio F with respect to a prior stage switch.

Abstract: A monolithic integrated circuit (IC) chip in which is formed a multi-driver power circuit, with each driver circuit including one output power transistor, is partitioned such that the power transistor of each driver circuit, formed in the IC, is spaced apart from those of any other driver circuit a distance sufficiently large to ensure the generation of a temperature differential between the power transistors of the different driver circuits when their power dissipation is different. A thermal sensor is formed in close proximity to each output power transistor, and as far away as possible from the other power transistors of the IC, whereby each thermal sensor is thermally, tightly, coupled to its associated power transistor. Each thermal sensor is electrically coupled to the base of its associated power transistor for controlling the conductivity of its associated power transistor when the power dissipation of its associated power transistor and its resulting temperature exceeds a predetermined level.

Abstract: A zener diode is connected at one end via a first impedance to a first power terminal. The base-to-emitter junctions of first and second transistors are connected in parallel between the other end of the zener diode and a second power terminal. The collector of the first transistor is connected to the one end of the zener diode to regulate the zener current and hence the zener voltage. A third transistor is coupled at its base to the one end of the zener and its emitter is connected to an output terminal to produce an output voltage which is a function of the zener voltage. The collector of the second transistor is connected to the emitter of the third transistor to pass a current through the third transistor which is approximately equal to the current through the first and second transistors whereby the base-to emitter junction of the third transistor and its temperature variations have little, if any, effect on the output voltage.

Abstract: A high frequency CMOS voltage level shifter providing either an inverted or noninverted signal output shifted in voltage level from an input signal. The level shifter includes two pairs of metal oxide semiconductor transistors with the transistors of each pair connected together and respectively connected to a first and second voltage source. The gates of a transistor in each pair are cross connected to the interconnected drains of the opposing transistor pair. First and second conducting elements are respectively connected to the cross connected transistor gates to discharge a transient capacitive gate charge present during output signal voltage level shifting.

Abstract: Each one of two switching transistors, driven by complementary input signals, has its conduction path connected between a different one of two output terminals and a first point of potential. Connected between each output terminal and a second point of potential are the conduction paths of a load transistor responsive to the signal at the other output terminal. A source follower transistor is connected to each output terminal. When the switching transistor connected to one output terminal is being turned-OFF, the source follower connected to that output terminal is turned-ON to enhance the voltage response at that terminal and to thereby accelerate the speed of response of the circuit and minimize its power dissipation.

Abstract: A timing system which includes a timer circuit, a source of first clock pulses for advancing the timer circuit, and a circuit for reading out the timer circuit in synchronism advanced therewith and where there is also included a second source of clock pulses asynchronous with respect to the first source of clock pulses, a synchronizing circuit is provided for storing an indication of the receipt of each second clock source pulse. Then the timer is advanced only when a pulse is produced by the first clock source and the indication is present that a signal has been produced by the second clock source.

Abstract: A sense amplifier having a transition point defining the signal level at its input above which it senses one binary condition and below which it senses the other binary condition includes precharge means for offsetting its input very slightly, above or below its transition point to place it in one of its two binary sensing states. The sense amplifier is suited for use with a memory array whose cells are coupled to the input of the sense amplifier via a single gating transistor which conducts in the (source or emitter) follower mode for the one binary condition and in the common (source or emitter) mode for the other binary condition. Following the precharge, the output of the memory cell is coupled to the input of the sense amplifier. For the cell storing the one binary condition for which the gating transistor conducts in the follower mode, the sense amplifier remains in the binary state to which its input was precharged.

Abstract: The circuit includes means for limiting the potential difference that can exist between corresponding electrodes of two input transistors interconnected to form a differential amplifier stage. The control electrode of each input transistor is coupled via a normally conducting gating transistor to its respective input terminal and via a normally non-conducting clamping transistor to a common point to which is connected one end (source or emitter) of the main conduction paths of the two input transistors. In response to an input signal at an input terminal having a polarity and a first value to turn off an input transistor, the gating transistor is turned off and decouples the control electrode of the input transistor from its corresponding input terminal. Then, as the input signal increases beyond the first value in a direction to further reverse bias the input transistor, the clamping transistor is turned on and clamps the control electrode of the input transistor to the common point.

Abstract: Photo sensitive elements formed on a surface of a substrate are arranged in rows and columns. Column conductors for selectively collecting the information contained in the photo elements are diffused along the length of each column in the same surface of the substrate as the photo elements. A barrier region is formed between the photo elements of each column and their associated column conductor for, normally, preventing leakage of charge from the diffused column conductors back into the photo elements. Row conductors, insulated from the surface of the substrate, are disposed transversely to the columns and lie over the rows of photo elements. Driving voltages applied to a row conductor either place the photo elements of that row in a signal collecting mode or else enable the collected signals in the elements of that row to surmount the barrier and flow into their corresponding column conductors.

Abstract: A field-effect device with closed floating gate geometry suitable for use as a storage element in a non-volatile memory array.

Abstract: Binary coded signals present on N input lines are decoded by means of N differential current switches. Each current switch is connected to a different one of the input lines and produces a group of 2.sup.(N-1) outputs in-phase with its input and a group of 2.sup.(N-1) outputs out-of-phase with its input. 2.sup.N conductors interconnect the outputs of the N switches to produce 2.sup.N decoded outputs, each of which represents a unique combination of the binary signals on the N input lines.

Abstract: A class of logic circuits in which different types of current switching logic gates are connected to different nodes of a current summing network for concurrently producing different logic functions of the same input variables. In one embodiment, N single-input current switches forming a threshold logic gate are operated with their inputs parallelling respective ones of an N-input current switch forming an emitter-coupled logic (ECL) OR-gate. An output current of the ECL gate is combined with the out-of-phase output currents of the threshold gate in a first current summing network, comprised of at least two resistors, for producing different logic functions of the signals applied to the N inputs. The in-phase output currents of the threshold gate are supplied to a second summing network for producing still different logic functions of the input signals. The different logic functions produced at the different nodes of the two summing networks may be further combined (e.g.

Abstract: The circuit includes a band selector which in one state controls the passage of a first band of frequencies (e.g. UHF signals) via a counter to a first input port of an Amplifier-Multiplexer (AMP/MUX) and which in another state controls the passage and amplification of a second band of frequencies (e.g. VHF signals) applied to a second input port of the AMP/MUX. When the band selector is in the one state, the stages of the counter are activated and only signals in the first band are coupled through the counter and through the AMP/MUX to additional count down stages connected to the output(s) of the AMP/MUX. In the other state, the stages of the counter are inactivated to prevent oscillations and feed through, and only signals in the second band are coupled through the AMP/MUX to the additional countdown stages.

Abstract: The sense circuit includes first and second inverters, connected at their inputs to first and second nodes, respectively. The inverters are selectively cross-coupled by means of transmission gates whose conduction paths are connected between the output of the first and second inverters, respectively, and the inputs of the second and first inverters, respectively. The control electrodes of the transmission gates are coupled to the first and second nodes whereby the transmission gates are turned on and off in response to the voltage levels at the first and second nodes. In the operation of the circuit a precharge voltage, having a polarity and magnitude to turn off the transmission gates, is applied to the two nodes. Subsequently, first and second current signals, having a polarity to generate potentials to turn on the transmission gates, are applied to the first and second nodes, respectively, altering the potentials at the nodes until the transmission gates are turned on.

Abstract: A gating means couples excitation signals to the input of an inverter which is connected between first and second power terminals. Positive feedback means is connected between the input and the output of the inverter. In response to an excitation signal, whose level is intermediate the levels of the operating voltages applied between the first and second power terminals, the inverter output is driven to the potential at one of the first and second power terminals while the potential at the other one of the first and second power terminals is applied to the inverter input. The gating means, conductive during transitions of the excitation signals from one level to another, does not conduct in the steady state condition, whereby a potential at the inverter input of higher amplitude than the excitation signals is not coupled back to the source of excitation signals.

Abstract: The operating potential to a storage element is supplied via an impedance element connected between a source of operating potential and a first power terminal of the storage element adapted to receive an operating potential. Information is written into the storage element via a gating transistor having its conduction path connected between an input line and a data input point to the storage element. Write circuitry includes means connected between the first power terminal and the input line. During a write operation, the write circuit, while applying the desired bit of information to the cell input, causes current to flow through the impedance element lowering the potential across the flip-flop until the desired bit of information is written into the cell.