Patents Represented by Attorney, Agent or Law Firm Harold L. Burstyn
  • Patent number: 5931959
    Abstract: Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ("FPGA"). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: August 3, 1999
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Kevin Anthony Kwiat
  • Patent number: 5907302
    Abstract: A signal processing system applies space-time adaptive processing ("STAP") to an airborne surveillance Doppler radar comprised of a single-channel, electronically scanned antenna. The STAP substantially improves signal-to-interference-plus-noise ratio ("SINR") by synthetically creating angular degrees of freedom, thereby improving the detection of weak targets.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: May 25, 1999
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: William L. Melvin, Jr.
  • Patent number: 5867443
    Abstract: A five-transistor static Random Access Memory (SRAM) cell accessed by a single bitline merged with heterogeneous memories, such as ROMs, EPROMs, EEPROMs, and DRAMs. Combined ROM and RAM cells have been included within a high performance signal processor. Advantages include area and power dissipation savings resulting from shared column bitlines, associated column decoders, and column sense amplifiers. This eliminates circuit duplication.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: February 2, 1999
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Richard W. Linderman
  • Patent number: 5848214
    Abstract: A Fiber Optic Plate is the substrate or part of the substrate in a multichip module. Multichip modules can be stacked to form layers of densely packed integrated circuit die. Optical signals carry data from one layer in the stack to one or more of the other multichip module layers or to peripheral devices physically separate from the stack. Data are transmitted at much greater speed by such optical signals than by traditional electronic interconnects. The Fiber Optic Plate guides the optical signals, minimizing signal crosstalk and allowing for many optical signals to occupy a small area on the module. A Fiber Optic Plate as all or part of the multichip module also provides a means to accurately align the individual modules in a stack.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: December 8, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Franz Haas, Paul R. Cook
  • Patent number: 5748653
    Abstract: The Vertical-cavity-surface-emitting Lasers with Optical Gain Control (V-LOGIC) form a family of integrated optical smart pixels for interconnect and signal processing applications. V-LOGIC devices consist of Vertical Cavity Surface Emitting Lasers (VCSELs) and In-Plane Lasers. (IPL) with cross-coupled cavities. The devices can operate in a digital, an analog or a hybrid mode. The IPLs either fully quench or modulate the VCSEL depending on whether the device is used in the digital or analog mode. In the Hybrid mode, one IPL serves as an enable input while another one modulates the VCSEL. The V-LOGIC devices can operate significantly faster than modulated lasers since, for the quenching phenomena, (1) the VCSEL carrier population is essentially constant and (2) the quenching is all-optical and does not require intermediate drive electronics. The family of devices solve the leading outstanding problems in optical switching and interconnect technologies.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: May 5, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Michael A. Parker, Richard J. Michalak, James S. Kimmet, Douglas B. Shire, Paul D. Swanson, Chung L. Tang
  • Patent number: 5748143
    Abstract: A signal processing system applies space-time adaptive processing ("STAP") to an airborne surveillance Doppler radar comprised of a single-channel, rotating antenna. The STAP substantially improves signal-to-interference-plus-noise ratio ("SINR"), thereby improving the detection of weak targets.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: May 5, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: William L. Melvin, Jr., Michael C. Wicks
  • Patent number: 5742045
    Abstract: Configurable Optical Gates (COGs) are used to transmit and receive optical signals similar to an interconnect device as well as perform a logic function on those signals (they are smart pixels). COGs consist of a laser with an intracavity modulator, an integrated current source and one or more integrated photodetectors to drive the modulators. The devices are monolithically integrated on MultiQuantum Well (MQW) heterostructure. Certain logic functions require that the bottom N- contact which is under individual devices be accessible and electrically isolated from neighboring devices. For this reason, the laser heterostructure is grown on a semi-insulating substrate. Each COG has a built-in light baffle that prevents the laser emission from coupling into the photodetectors. The optical detection of the COG can be disabled during fabrication and the device can be directly modulated by conventional electronics.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: April 21, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Michael A. Parker, Paul D. Swanson, Stuart I. Libby, James S. Kimmet
  • Patent number: 5737192
    Abstract: Chip-like stacks of thinned chips are mounted in wells etched into a substrate. A"chip-like" stack is a stack of chips, which in the aggregate have a height approximately equal to that of a single conventional chip. These chip-like stacks are mounted in a variety of packages. In a preferred embodiment, the stacks are mounted in wells within the substrate of an integrated circuit and the stack is provided with a patterned overlay so that all the circuit connections can be made from the upper surface of the stack. The patterned overlay is protected by a planar insulator. A plurality of substrates may be stacked, one upon the other.
    Type: Grant
    Filed: July 10, 1995
    Date of Patent: April 7, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Richard W. Linderman
  • Patent number: 5706013
    Abstract: Apparatus and method for improving detection of targets in a radar system that employs adaptive filtering. A nonhomogeneity detector eliminates nonhomogeneous signals from the population of signals received. An adaptive filter weight controller estimates covariance matrices from only homogenous signals. Thus the apparatus and method improves the probability of detecting the presence or absence of a target at the same time that it decreases the probability of a false alarm by improving the performance of an adaptive filter. Though developed for airborne radar, the apparatus and method may be applied to the processing of any image.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: January 6, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: William L. Melvin, Michael C. Wicks, Pinyuen Chen
  • Patent number: 5675521
    Abstract: The disclosure describes a method for performing thermal reliability analysis of electronic devices such as multichip modules. The method supports the reliabilty of multichip technology during the design phase by integrating traditional thermal analysis techniques, such as Finite Element Analysis with artificial intelligence techniques. Specifically, the use of object oriented programming, blackboard architecture and knowledge sources (based on expert systems) allow the computer to perform lower level reasoning associated with the development of the finite element mesh. The use of software, called Intelligent Multichip Module Analyzer, results in a great reduction in the amount of time required to model and to perform thermal analysis of multichip modules. This allows the analysis to be integrated with the design process so that reliability assessment can be accomplished when it can best affect the final design.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: October 7, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Douglas J. Holzhauer, Dale W. Richards, Ian R. Grosse, Daniel D. Corkill, Prasanna Katragadda
  • Patent number: 5668657
    Abstract: The unique properties of quadratic lead lanthanum zirconate titanate (PLZT) compositions make feasible the development of phased array optical scanners. Two implementations of integrated PLZT phased array scanners as two-port and three-port devices are presented. The three-port offers a significant reduction in the maximum electrode voltage required to effect a specific scan angle. The maximum electrode voltage of the PLZT phased array scanner is characterized in terms of the resolution of the scanner.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: September 16, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Pierre J. Talbot
  • Patent number: 5666518
    Abstract: Apparatus and method for replacing the traditional amplifications by rime delays in a neural network that can be trained to analyze temporally-related patterns. Time delays comprise the synapses between feeder and stimulus cells in the network. The result is a multi-temporal trainable delay neural network.
    Type: Grant
    Filed: June 26, 1995
    Date of Patent: September 9, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Eric J. Jumper
  • Patent number: 5657267
    Abstract: Individual cells in a memory array are structured and interconnected to permit detection and identification of the locations of errors known as Single Event Upsets (SEUs), with the correction and identification of an affected cell made using only a single parity bit for a group of cells in a memory array, eliminating the necessity for reading an entire memory in order to detect SEUs immediately, and eliminate large numbers of non-useful correction-code cells in order to increase the net useful density of cells in a memory and tolerate a larger rate of SEU events than for previous methods, additionally eliminate the need for purification of packaging materials for memory arrays by removing most radioactive materials and providing a further economic benefit by eliminating the need for organic coatings, which can cause reliability hazards, and to block alpha particles originating in packaging.
    Type: Grant
    Filed: October 5, 1995
    Date of Patent: August 12, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Mark W. Levi
  • Patent number: 5650629
    Abstract: An alignment mark and pattern is disclosed for use on semiconductor substrates which are to be patterned in an electron lithography machine. The detector includes two interleaved N-well portions mounted on a P-substrate. The interleaved "fingers" of the N-well portions are spaced to provide narrow gaps which are approximately the width of a projected electron beam. When the beam is located within the gap (or gaps) the projection is in alignment.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: July 22, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Mark W. Levi
  • Patent number: 5416662
    Abstract: A single three-terminal chip-type surge absorber combines two or three semiconductor surge-absorbing elements with three electrode plates and resin-molding the combination. When more lines must be connected to an electronic device subject to a voltage surge, instead of mounting a plurality of surge-absorbing elements, which requires a substantial space and many mounting steps, a single surge absorber with a plurality of surge absorbing elements absorbs the voltage surge.
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: May 16, 1995
    Inventors: Koichi Kurasawa, Takaaki Ito
  • Patent number: 5404126
    Abstract: A fuse resistor protects a circuit from a surge, an overcurrent from an unexpected connection, or the like. When a continuous overvoltage higher than a predetermined value is applied to the circuit, the heat from a heat-generating resistant film fractures an insulating substrate of the fuse resistor to open the circuit. Changing the minimum current to which the fuse resistor responds, by modifying a cutout or notch on the substrate, makes it possible to use the fuse resistor anywhere in the circuit. A discharging-type surge absorbing element with a security mechanism that includes the fuse resistor can thus provide protection against a surge or a continuous overcurrent that is more than the rated value of the fuse resistor.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: April 4, 1995
    Assignee: Okaya Electric Industries Co., Ltd.
    Inventors: Yoshito Kasai, Yoshiro Suzuki, Akihiko Ikazaki
  • Patent number: 5402120
    Abstract: A navigation system mounted on a vehicle displays a primary direction indication image on a display unit. This primary direction indication image has a proximal portion that represents a road along which the vehicle is now moving and a direction indication portion that represents a road which the vehicle is to enter at the next intersection. One or more auxiliary direction indication images, with direction indication portions that represent other roads connected to the next intersection, are displayed on the display unit together with the primary direction indication image. The direction indication portion of the auxiliary direction indication image extends from the distal end of the proximal portion of the primary direction indication image.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: March 28, 1995
    Assignee: Zexel Corporation
    Inventors: Takao Fujii, Tatsuhiko Abe
  • Patent number: 5396038
    Abstract: A key stem of a keyboard switch includes an outer slide and an inner slide. When a key top is struck, the outer slide slides inside of an outer guide, and the inner slide slides inside an inner guide. A first moment point is developed between the outer slide and the outer guide, while a second moment point is developed between the inner slide and the inner guide. A taper at the bottom of the outer slide prevents the second moment point being developed in that location. The reduced horizontal distance between the two moment points helps prevent binding of the key when an actuating force is applied off the axis of the key top. A relationship is disclosed for avoiding sticking or binding in which the horizontal distance between the two moment points, times a coefficient of friction, is less than the vertical distance between the planes of the two moment points.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: March 7, 1995
    Assignee: SMK Co., Ltd.
    Inventor: Kazunori Yamada
  • Patent number: 5393058
    Abstract: A simulated golf game in which a remotely controlled golfer plays on a miniature course, The physical mechanisms and methods of control of the game are directed to heighten its realism. The course has all the characteristics of a real golf course, e.g., hills, valleys, sand traps, and trees. The golfer is a model human figure who plays a miniature ball free that is to roll anywhere on the course. The golfer is remotely controlled through an overhead gantry positioning mechanism that connects to the golfer's back by way of a small-diameter rigid tube. The gantry simulates walking by moving the tube, with the golfer attached, about the golf course. Animation of the golfer itself (bending at the waist, swinging the club, etc.) is effected by a set of electric motors driving cables running inside the tube. Many of the motors are operated simultaneously to give the golfer a lifelike look. The motor operations are controlled by a computer.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: February 28, 1995
    Inventors: Bruce Rowland, Dean Rowland
  • Patent number: 5394333
    Abstract: A hybrid vehicle navigation system employs both GPS and dead reckoning sensors, working in parallel, to produce a sensed and a calculated position, respectively. The sensed and the calculated positions are compared to a road data base to determine separate correction factors required to correct the sensed and the calculated positions. In one embodiment, the system employs either the sensed or calculated position for navigation depending on which has the smaller correction factor.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: February 28, 1995
    Assignee: Zexel USA Corp.
    Inventor: Wei-Wen Kao