Abstract: A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the number of distinct memory portions. The packet header processing unit is configured to retrieve the different types of descriptor information from the number of distinct memory portions and to generate header information from the different types of descriptor information.

Abstract: Methods and devices for processing packets are provided. The processing device may include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data units.

Abstract: Techniques for grouping hyperlinked documents are provided. Links near or in the neighborhood of the hyperlinked documents are analyzed in order to group the hyperlinked documents by topic. For example, links that are search results can be grouped by identifying other hyperlinked documents that have multiple forward links to the search results. The search results can then be grouped according to the forward links of the other hyperlinked documents.

Abstract: A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a packet, the packet may be unloaded from the first and second buffer while a new packet is simultaneously loaded to the packet header processing engine.

Abstract: In an ATM exchange, a cell transmission control section transmits an ATM cell to a transmission path of an ATM network A traffic monitor monitors traffic of the cell transmissions. A statistical process section performs a temporal statistical process on the result of the traffic monitoring using a clock and a memory. A CAC produces an instruction for traffic control over a transmission terminal based on the result of the statistical process. A UPC controls traffic of a transmission path from the transmission terminal in accordance with the instruction.

Abstract: A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

Abstract: The invention provides an ATM switch which realizes hierarchical shaping for each virtual channel and each virtual path with a simple configuration. Cells are sent from cell buffers of an ATM core switch by FIFO operation to output side connection information application sections of output side circuit interfaces. In each of the output side circuit interfaces, the output side connection information application section acquires connection information such as a service class based on an intra-switch connection identification number applied to each cell and applies the connection information to the cell. An output cell buffer queues cells for each virtual channel. A VC cell rate control section reads out cells from the output cell buffer in accordance with the connection information and performs traffic priority control and rate control of the cells to be outputted.

Abstract: A reorder engine classifies information relating to incoming data items as belonging to either a first, second, or third region. The information relating to the data items may arrive at the reorder engine out of order. The data items each include a sequence number through which the reorder engine may reconstruct the correct order of the data items. Based on the classification, the reorder engine may either process the data items normally or drop certain ones of the data items. The majority of incoming data items will fall in the first region and are processed normally. Data items arriving in the second region indicate that a previous data item is late or delayed. If this previous data item is delayed but does eventually arrive, it will arrive in the third region and is simply ignored.

Abstract: A network system uses a management routing instance to route management information between elements involved in management of the system. The system registers each element in the management routing instance when the element comes on line. Based on the management routing instance, the system creates management forwarding tables. The system then uses the management forwarding tables to route management information between the elements. Multiple systems, for example systems connected by a network, may exchange management routing instance information to allow elements in different systems to communicate management information with each other.

Abstract: A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.

Abstract: A base station may include an interface section, a master receive processor, and a slave receive processor. An interface section may receive data from a higher rank station in the mobile communication system, the data may be received over a leased line. The master receive processor may receive the data from the higher rank station, determine whether the data from the higher rank station includes information destined for the base station, and terminate the data at the base station when the data from the higher rank station is determined to include information destined for the base station. The slave receive processor may receive the data from the higher rank station, determine whether the data from the higher rank station includes information destined for another base station, and transmit, over the leased line, the data to the another base station when the data from the higher rank station is determined to include information destined for the another base station.

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: A system and method for a network security system are provided. The method includes providing a master device and a backup device within a cluster of network security devices, providing the backup device with state information for the master device, detecting failure in the cluster and using the state information to recover from the failure.

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract: A system processes data corresponding to multiple data streams. The system includes multiple queues that store the data, stream-to-queue logic, dequeue logic, and queue-to-stream logic. Each of the queues is assigned to one of the streams based on a predefined queue-to-stream assignment. The stream-to-queue logic identifies which of the queues has data to be processed. The dequeue logic processes data in the identified queues. The queue-to-stream logic identifies which of the streams correspond to the identified queues.

Abstract: A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

Abstract: A computer-implemented method for determining whether a target text-string is correctly spelled is provided. The target text-string is compared to a corpus to determine a set of contexts which each include an occurrence of the target text-string. Using heuristics, each context of the set is characterized based on occurrences in the corpus of the target text-string and a reference text-string. Contexts are characterized as including a correct spelling of the target text-string, an incorrect spelling of the reference text-string, or including an indeterminate usage of the target text-string. A likelihood that the target text-string is a misspelling of the reference text-string is computed as a function of the quantity of contexts including a correct spelling of the target text-string and the quantity of contexts including an incorrect spelling of a reference text-string. In one application, the target text-string is received in a search query, the search executed following a spell-check.

Abstract: An ATM switching system 1 is provided with an ATM switch 11, a reserved connection memory 12 for storing reserved connection information, a call history memory 13 for maintaining call histories of requests for connection from subscriber's terminal units 2?1 to 2?n, and a call-signal processing section 15. The call-signal processing section 15 generates a request for connection with respect to a trunk ATM switching network 3 by the use of the call histories in the call history memory 13 in the case where no call was issued from the subscriber's terminal units, and stores response results thereof in the reserved connection memory 16. Thereafter, when there was a call from the subscriber's terminal units 2?1 to 2?n, and contents of the request for connection thereof are the same as the reserved connection information, which has been stored in the reserved connection memory 16, processing for connection is executed by the use of the reserved connection information.

Abstract: A switch fabric includes input links, output links, and at least one switching element. The input links are configured to receive data items that include destination addresses. At least some of the data items have different priority levels. The output links are configured to output the data items. Each of the output links is assigned multiple ones of the destination addresses. Each of the destination addresses corresponds to one of the priority levels. The switching element(s) is/are configured to receive the data items from the input links and send the data items to ones of the output links without regard to the priority levels of the data items.