Patents Represented by Attorney, Agent or Law Firm Hayes, Soloway, Hennessey, Grossman & Hage
  • Patent number: 6306188
    Abstract: Method for the fabrication of filters with deep folds connecting of opposed sides of the filter to prevent blow-out, by welding intermediate distance elements to the filter material on each side. The distance elements include bridges and/or connections between parts welded to the difference filter sides. The bridges are extendable to different lengths at different locations in the filter.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: October 23, 2001
    Assignee: Camfil AB
    Inventor: Niclas Karlsson
  • Patent number: 6307698
    Abstract: An amplitude comparator compares to one another amplitudes of data items, which have been read by read heads and amplified by amplifiers. An error identification circuit detects a read level lowering in the read heads according to the result of the comparison. A signal processor references the detection result of the error identification circuit if a read error is detected. If any of the read units has a lowered read level, the cause of the read error is determined to be in that read unit. If none of the read heads has a lowered read level, it is determined that the read error has been caused by other than the read heads.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: October 23, 2001
    Assignee: NEC Corporation
    Inventor: Tadashi Ishitsuka
  • Patent number: 6303778
    Abstract: The present invention concerns a new fractionated polydisperse carbohydrate composition having the following definition: an av. DP which is significantly higher than the av. DP of a native polydisperse carbohydrate composition, significantly free of low molecular monomers, dimers, and oligomers, significantly free of impurities chosen among the group consisting of colourings, salts, proteins and organic acids, significantly free of technological aids such as solubility affecting products. The present invention concerns also the preparation process of the composition according to the invention.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: October 16, 2001
    Assignee: Tiense Suikerrafinaderij N.V.
    Inventors: Georges Smits, Luc Daenekindt, Karl Booten
  • Patent number: 6303422
    Abstract: A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd1 and Qd2, a pair of transferring transistors Qt1 and Qt2, high resistance loads R1 and R2, a pair of bit lines BL1 and BL2, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: October 16, 2001
    Assignee: NEC Corporation
    Inventors: Tomohisa Abe, Masaru Ushiroda, Toshio Komuro
  • Patent number: 6303487
    Abstract: In a method for forming an air gap in an insulating film between adjacent interconnection conductors in a semiconductor device, a substrate having a first insulator film and a plurality of lower level interconnection conductors formed separately from each other on the first insulator film is set in a chemical vapor process machine. A second insulator film is deposited to completely cover the plurality of lower level interconnection conductors and the first insulator film in a chemical vapor process under the condition that a growth speed in a vertical direction perpendicular to a principal surface of the substrate is lower than a growth speed in a horizontal direction in parallel to the principal surface of the substrate, until the second insulator film has such a thickness that an air gap is formed within the second insulator film between the adjacent interconnection conductors.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: October 16, 2001
    Assignee: NEC Corporation
    Inventor: Masaki Kagamihara
  • Patent number: 6303983
    Abstract: A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The tie bars are provided to outer lead portions of the lead frame to prevent resin leakage during resin encapsulation, and are cut and removed in a finishing step of resin encapsulation. A plating surface is formed on a sectional surface of each of the tie bars. A semiconductor device manufacturing method and apparatus are also disclosed.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: October 16, 2001
    Assignee: NEC Corporation
    Inventor: Masahiro Koike
  • Patent number: 6300635
    Abstract: An X-gamma dosimeter responsive to low energy values includes X and gamma radiation detectors responding differently in relation to the dose absorbed at low energy. One detector overestimates the dose absorbed with regard to human tissues, while the other detector underestimates the absorbed dose. An electronic processor combines signals supplied by both detectors, the combination being optimized so as to report accurately the dosimetric quantity within a large energy range.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 9, 2001
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Andrea Brambilla, Thierry Pochet
  • Patent number: 6298741
    Abstract: An actuator for driving two separate gear trains having separate loads. The actuator includes: a drive motor; a drive gear attached to an output shaft of the drive motor; and first and second mating gears in meshing engagement with the drive gear. The first mating gear is axially fixed relative to the drive gear and adapted for driving the first gear train. The second mating gear is axially movable relative to the drive gear and adapted for driving the second gear train. Upon application of power to the drive motor, the first mating gear drives the first gear train, and the second mating gear drives the second drive train. The second mating gear is adapted to travel axially relative to the second gear train for disengaging therefrom when a load causes the second gear train to stall. The first mating gear may continue to drive the first gear train to stall.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: October 9, 2001
    Assignee: Joseph Pollak Corporation
    Inventor: Henry Minasian
  • Patent number: 6300186
    Abstract: There is provided a method of manufacturing a semiconductor device having a MOS transistor formed on a silicon substrate, and a stacked capacitor constituted by an information storage electrode provided above the MOS transistor through an insulating interlayer and a counter-electrode separated from the information storage electrode due to the presence of a capacitor insulating film. In this method, the capacitor is formed by adding an impurity in a silicon oxide film which is formed on the insulating interlayer and used to shape the information storage electrode, and performing etching by using a chemical solution containing phosphoric acid, sulfuric acid, nitric acid, or a solution mixture thereof, or a chemical solution containing a solution mixture of an aqueous ammonia solution and a hydrogen peroxide solution to selectively remove the silicon oxide film added with the impurity.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventors: Toshiyuki Hirota, Shuji Fujiwara
  • Patent number: 6300803
    Abstract: A phase-comparison circuit includes (a) a first PNP transistor, (b) a second PNP transistor, (c) a third NPN transistor electrically connected to both a collector of the first PNP transistor and a base of the second PNP transistor, and (d) a constant current source electrically connected to an emitter of the third NPN transistor. The phase comparison circuit compensates for an offset current between a reference current and an output current, and as a result, can properly operate at a low voltage.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventor: Naohiro Matsui
  • Patent number: 6296804
    Abstract: A continuous process and apparatus for producing oriented plastic tube comprising the steps of extrusion, temperature conditioning, diametrical expansion and cooling, characterized by the step of inducing axial draw of the tube between first and second haul-off means located upstream of the expansion step.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: October 2, 2001
    Assignees: Vinidex Pty Limited, Uponor Innovation AB
    Inventors: Peter Glanville Chapman, Jyri Jarvenkyla
  • Patent number: 6291890
    Abstract: A semiconductor device has a thin semi-insulating polycrystalline silicon (SIPOS) film on the surface of a silicon substrate having a diffused region therein. The SIOPS film is thermally treated at the bottom of a via-plug of an overlying metallic film to form a metallic silicide for electrically connecting the via-plug with the diffused region, whereas the SIPOS film is maintained as it is for insulation on a dielectric film. The SIPOS film protects the diffused regions against over-etching to thereby improve the junction characteristics and provide a larger process margin for contacts between the metallic interconnects and the diffused regions.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: September 18, 2001
    Assignee: NEC Corporation
    Inventor: Koji Hamada
  • Patent number: 6288407
    Abstract: An electron beam-writing apparatus comprising a first beam-shaping aperture means and a second beam-shaping aperture means, wherein the first and/or second beam-shaping aperture means has an aperture(s) of a shape(s) corresponding to the desired patterns to be written on a semiconductor substrate; and an electron beam-writing method of improved throughput using the apparatus.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventor: Katsuyuki Itoh
  • Patent number: 6287750
    Abstract: In a method of manufacturing a semiconductor device, an inorganic insulating layer is formed to cover a conductive layer, a polyimide layer is formed to cover the inorganic insulating layer, and a photo-resist layer is formed to cover the polyimide layer. An opening portion is formed by use of development or a wet etching to pass through the photo-resist layer and the polyimide layer to the inorganic insulating film. Then, after the photo-resist layer is removed, heat treatment is performed of the polyimide layer. Subsequently, the inorganic insulating film is etched using the polyimide layer having the opening portion as a mask. The photo-resist layer has a film thickness in a range of 4 to 10 &mgr;m, and the polyimide layer has a film thickness in a range of 5 to 20 &mgr;m.
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventor: Michio Sakurai
  • Patent number: 6287929
    Abstract: In accordance with the above first embodiment of the present invention, after a base polysilicon film has been grown, a lump anneal is carried out because of an extremely small variation to the silicon dioxide film. Subsequently, a buffered fluorine acid is used which has a large selective etching ratio of the silicon oxide film to the polysilicon film to side-etch the silicon oxide film in the horizontal direction by a predetermined width before the base impurity BF2+ is implanted and then the emitter polysilicon film is formed. For those reasons, a variation in distance between the n+-substrate and a collector is small. The base width “WB” of the base region is not varied, whereby variations in high frequency performance of the bipolar transistor are suppressed.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventor: Hiroshi Kato
  • Patent number: 6287915
    Abstract: In a flash memory that has a floating gate that is formed by a polysilicon layer having grains, a gate electrode is formed on a gate oxide film that is provided on a semiconductor substrate, this gate electrode being formed as a multilayer structure by a polysilicon layer that has grains and at least one more polysilicon layer.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventor: Satoru Muramatsu
  • Patent number: 6288452
    Abstract: As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a (#) shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a (#)-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventor: Masahiro Komuro
  • Patent number: 6284244
    Abstract: Mediating the effects of alcohol consumption by orally administering an active dry yeast containing alcohol dehydrogenase to a person prior to or simultaneously with consumption of an alcohol-containing beverage to oxidize a portion of the alcohol while it is still in the stomach of the person is described.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: September 4, 2001
    Inventor: Joseph L. Owades
  • Patent number: 6285161
    Abstract: A balanced battery cell charging circuit is provided. The circuit includes a comparator for comparing the voltage of a battery cell to a predetermined threshold voltage. If the cell voltage exceeds the threshold value, a bleeder current is generated. In one preferred embodiment, the bleeder current is subtracted from the charging current. In another embodiment, the bleeder current is multiplied, and the multiplied bleeder current is subtracted from a total charging current supplied to the cell. To control the charger circuit, current feedback is provided by monitoring the bleeder current generated against a maximum bleeder current, and adjusting the charging current accordingly. The topology of the present invention provides active cell balancing between cells of a battery, and low total power dissipation of the circuit.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: September 4, 2001
    Assignee: O2 Micro International Limited
    Inventor: Serban-Mihai Popescu
  • Patent number: 6280816
    Abstract: An automotive interior trim panel has an outer flexible skin that overlies a rigid backing panel formed with a foam entry hole through which foam precursors are poured into a space between the skin and panel and they react and expand to generate a foam layer within the space. Tab projections are carried by the panel and extend into the foam space to at least partially cover the opening and provide rigid backing support for foam expanding in the region of the entry hole to control the density of the foam in this entry hole region such that it conforms more closely with the density of the immediate surrounding foam.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: August 28, 2001
    Assignee: Textron Automotive Company Inc.
    Inventor: David R. McCooey