Abstract: A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed.
Abstract: Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.
Abstract: A system and method for managing multiple message format communication that may provide the ability to route, transform, and augment inbound messages, so that virtually any outbound message may be constructed.
Type:
Grant
Filed:
May 2, 2005
Date of Patent:
December 11, 2012
Assignee:
American Airlines, Inc.
Inventors:
Monty Fouts, Richard Bowman, Mark Hanson
Abstract: The present invention provides a technique for percutaneous intramedullary fixation. A protective outer sheath is provided for internal fixation of the proximal tibia. Additionally, a unique intramedullary plate is provided that is adapted for percutaneous insertion into the intramedullary canal of a long bone. A plate holder is also provided that may be utilized through the outer sheath to drive and position a fixation plate within the intramedullary canal.
Abstract: The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.
Abstract: The present disclosure provides an illuminating system including a light emitting device and a luminescent material disposed approximate the light-emitting device. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium (Ce3+) and lithium (Li+).
Abstract: A method for interworking supplementary call services between different VOIP protocols is provided. The method comprises receiving, during a call between a first end device and a second end device, a first message in a first protocol format for the second end device to transfer the call to a third end device; determining interworking information to interwork the first message to a second message in a second protocol format; generating the second message based on the interworking information, such that the second message initiates the call transfer to the third end device.
Type:
Grant
Filed:
February 5, 2007
Date of Patent:
December 11, 2012
Assignee:
Cisco Technology, Inc.
Inventors:
Parameswaran Kumarasamy, Paul R. P. Chu, Jayesh Chokshi, Sunila R. Ainapure, Sandeep Singh Kohli, Sabita Jasty, Vijay Kannan
Abstract: A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.
Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
Abstract: Proposed is a pyrolysis reactor for processing solid municipal and domestic wastes by means of a pyrolytic reaction in the pyrolysis chamber without access of oxygen to the reaction system. The reactor is characterized by containing two waste-feeding screws which have tapered shapes, a gap between the outer surfaces of the threads, are inclined in the vertical plane and converge towards each other in a horizontal plane in the direction from the inlet to the outlet end. The gap is adjustable with diminishing toward the outlet end.
Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.
Type:
Grant
Filed:
June 15, 2011
Date of Patent:
December 11, 2012
Assignee:
Dell Products L.P.
Inventors:
Ardian Darmawan, Curtis Ray Genz, Clay Phennicie
Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.
Abstract: A system, according to one embodiment, includes a hybrid account provided by an issuer to a user, the hybrid account having a balance, the balance being either positive, zero, or negative; and a financial instrument including a hybrid card, the hybrid card providing access to the hybrid account, in which transactions using the hybrid card provide interchange income to the issuer, the issuer charges interest to the hybrid account when the balance is negative, and the issuer pays interest to the hybrid account when the balance is positive.
Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.
Abstract: Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.
Abstract: A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities.
Inventors:
Jinesh Balakrishna Pillai Kochupurackal, Willem Frederik Adrianus Besling, Johan Hendrik Klootwijk, Robert Adrianus Maria Wolters, Freddy Roozeboom
Abstract: A battery and speaker mounting apparatus includes a base member including a battery socket positioned adjacent a support surface on the base member, and a speaker chamber defined by the base member and separated from the battery socket by the support surface. A speaker module may be mounted in the speaker chamber, and a battery may be coupled to the battery socket.