Abstract: A wireless system includes a network of base stations for receiving uplink signals transmitted from a plurality of remote terminals and for transmitting downlink signals to said plurality of remote terminals using a plurality of channels. A plurality of antenna elements at each base station receives uplink signals, and a plurality of antenna elements at each base station for transmits downlink signals. A signal processor at each base station is connected to the receiving antenna elements and to the transmitting antenna elements for determining spatio-temporal signatures. Spatio-temporal multiplexing and demultiplexing functions are provided for each remote terminal antennae for each channel, and a multiple base station network controller optimizies network performance, whereby communication between the base stations and the plurality of remote terminals in each of the channels can occur simultaneously.

Abstract: A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.

Abstract: The present invention provides for a novel programming operation of a programming portion of an FPGA interconnect cell. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors have N+ source/drain regions and share a common N+ source/drain region. A first interconnection line is connected to the N+ source/drain region of the EPROM transistor and a second interconnection line connected to the N+ source/drain region of the select transistor. By setting the first interconnection line and the second interconnection line at respective voltages so that majority charge carriers flow from the N+ region of the EPROM transistor through the common N+ region to the N+ source/drain region of the select transistor during a programming operation of a selected FPGA interconnect cell in an array of such cells, drain disturb effects on the unselected cells are avoided.

Abstract: A pipelined microprocessor is provided with a queuing stage between an instruction fetch stage and an instruction decode stage to facilitate branch instructions and to receive instructions from the fetch stage when the decode stage is stalled. If a branch is incorrectly anticipated the queuing stage has nonbranch sequential instructions for the decode stage while the fetch stage is restarted at the nonbranch sequential instruction stream.