Abstract: In the fabrication of an interconnection package for a plurality of semiconductors or integrated circuit chips wherein a multi-layered glass or glass-ceramic superstructure with a multi-layered distribution of planar conductors is formed by a process forming vertical conductive interconnection or studs between planar conductor layers, by pre-forming a via configuration in each glass or glass-ceramic layer at the interconnection points followed by depositing the conductive studs therein. The via configuration is formed by defining a desired pattern of vias, and ablating the vias through the top of and through the glass or glass-ceramic layer, using an ultraviolet laser. The vias may be stepped-shoulder or counter-bored by using a two mask operation.

Abstract: Pinhole-free thin films deposited by glow discharge or plasma polymerization of organosilanes, organosilazones and organosiloxanes for use as reactive ion etch oxygen barriers in multilayer resist structures, of lift-off masks, for fabrication of semiconductor devices, such as integrated circuits. The process includes deposition of thin plasma polymerized organosilicon barrier film over a radiation insensitive polymeric base layer previously coated on a substrate, followed by thermal annealing of the plasma polymerized barrier layer, over which is then coated a radiation sensitive resist layer. After definition of the desired resist pattern by imagewise exposure and development, the image is etch transferred into the barrier layer by reactive sputter etching in a fluorine containing ambient, and subsequently transferred into the base layer, down to the substrate, in an oxygen plasma, during which time the plasma deposited film functions as an oxygen barrier.

Abstract: Pinhole-free thin films deposited by glow discharge or plasma polymerization of organosilanes, organosilazones and organosiloxanes for use as reactive ion etch oxygen barriers in multilayer resist structures, of lift-off masks, for fabrication of semiconductor devices, such as integrated circuits. The process includes deposition of thin plasma polymerized organosilicon barrier film over a radiation insensitive polymeric base layer previously coated on a substrate, followed by thermal annealing of the plasma polymerized barrier layer, over which is then coated a radiation sensitive resist layer. After definition of the desired resist pattern by imagewise exposure and development, the image is etch transferred into the barrier layer by reactive sputter etching in a fluorine containing ambient, and subsequently transferred into the base layer, down to the substrate, in an oxygen plasma, during which time the plasma deposited film functions as an oxygen barrier.

Abstract: There is disclosed a method of selectively metallizing a ceramic substrate provided with a metallization pattern according by photoresist processing. A first layer of photoresist is blanket deposited over the substrate exposed through a coarse block out mask, and developed in order to protect those areas of the metallization pattern not to be covered with metal. A blanket metal layer is then formed over the entire substrate surface. A second layer of photoresist is deposited, exposed through a customized mask of the metallization pattern, and developed. The exposed metal is etched and the remaining first and second photoresist layers are removed, leaving a coating of metal only at desired locations.The method may be used for the heavy gold deposition over the Engineering change pads used as a standard in multilayer ceramic substrates.

Abstract: This invention relates more particularly to an electron-gun metal evaporation system for solder (lead/tin, lead/indium) deposition upon integrated circuit chips. This system utilizes a crucible comprised of a tantalum bent-cone V-shaped liner or cup seated in spaced relationship in a recess of a copper hearth.

Abstract: An insulating or masking film for semiconductor devices formed by curing applied coatings of biphenylene end-capped quinoxaline polymers.

Abstract: A method of coating or cladding existing metallurgical features of a dielectric substrate by sequentially blanket coating the substrate, inclusive of the metal features, with discrete levels of diverse metals forming alloy systems exhibiting a minimum in the liquidus curve, followed by heating the substrate to a temperature (T.sub.H) at or slightly above the lowest liquidus temperature in the phase diagram of the alloy system and below the melting points of the metal components. During heating to temperature, the metals interdiffuse forming a range of compositions changing with time to form liquid alloys which moves to the substrate surface where it wets and bonds to the metallic features while dewetting the bar substrate surface portions. On cooling the non-adhering portions the alloy can be suitably removed from the substrate surface, as by ultrasonic action, leaving an alloy of the metals strongly bonded only to the pre-existing metallurgical features.

Abstract: A method of coating or cladding existing metallurgical features of a dielectric substrate by sequentially blanket coating the substrate with two discrete levels of diverse metals having differential in melting point and forming a continuous series of alloy solid solutions whose solidus curve lies intermediate the melting points of the two component metals, with the metal having the lower melting point disposed adjacent said substrate, followed by heating of the substrate to a temperature slightly above melting point of the lower melting metal but not exceeding the liquidus temperature of a completely homogenized alloy corresponding to amounts of the metals deposited, with cooling of the substrate to delaminate the metal coatings on the bare surface areas of said substrate, and mechanically removing said delaminated metal coatings to retain a bonded cladding comprised of said metals on said metallurgical features.

Abstract: Pinhole-free thin films deposited by glow discharge or plasma polymerization of organosilanes, organosilazones and organosiloxanes for use as reactive ion etch oxygen barriers in multilayer resist structures, of lift-off masks, for fabrication of semiconductor devices, such as integrated circuits. The process includes deposition of thin plasma polymerized organosilicon barrier film over a radiation insensitive polymeric base layer previously coated on a substrate, followed by thermal annealing of the plasma polymerized barrier layer, over which is then coated a radiation sensitive resist layer. After definition of the desired resist pattern by imagewise exposure and development, the image is etch transferred into the barrier layer by reactive sputter etching in a fluorine containing ambient, and subsequently transferred into the base layer, down to the substrate, in an oxygen plasma, during which time the plasma deposited film functions as an oxygen barrier.

Abstract: The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF.sub.4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.

Abstract: A resist system for semiconductor device fabrication comprised of bottom positive resist layer of a diazoquinone/novolak resist applied to a substrate and overcoated with a like or different diazoquinone/novolak top resist layer which has been sensitized with pyrene and/or its derivatives.

Abstract: A plasma reactor comprises a reaction chamber having two plate-shaped electrodes arranged parallel to and above each other, whereby the substrates are supported on the lower electrode and this electrode is additionally provided with a center opening (5) through which gas is fed into the electrode space or which is evacuated from it, and where (a) the upper electrode is connected to a high frequency AC or RF voltage and (b) which has no electrode material in the regions opposite the substrates and (c) where their position and shape are determined by the substrates on the lower electrode, causing the electric field in the electrode space to be selectively weakened at at least above the substrates.

Abstract: Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

Abstract: Maskless technique for plating a protective metal layer on existing metallurgical pattern supported on a dielectric substrate by blanket coating said metal layer over said substrate, heating to diffuse the metal into said pattern, cooling to spall the metal on the non-patterned portions of the substrate surfaces by the stresses induced from the differences in the thermal contraction differentials between the metal and the substrate, and mechanically removing the metal layer from the non-patterned substrate surfaces. Optionally, the metal layer can also be blanket coated with a passivating metal film with interdiffusion between them at their interface during the noted heating step. In application to support carriers for mounting of semiconductor devices, the substrate will comprise an alumina based ceramic, the pattern will comprise a molybdenum based metal, and the protective metal layer can comprise a nickel based metal. In this application, the second passivating metal film can comprise gold.

Abstract: A controlled geometric configuration of contact pads for securing solder mounds to an integrated circuit chip which reduces cracking of brittle passivating coatings in fabrication of components.

Abstract: A reactor comprising a plate-shaped cathode that is horizontally arranged and connected to an alternating voltage, in a ground connected casing, and gas inlet and gas outlet lines. The cathode is equipped with means for generating local magnetic fields restricted to the region of the individually supported substrates. The cathode can be furthermore have holes or openings in which are arranged substrate holders shiftable or movable vertically to relate to the substrate surface.The substrates are etched in the reactor by means of a plasma which is produced from at least one reactive gas. Each substrate is exposed to at least one local magnetic field. If a mostly chemically etchable material is to be etched in the presence of a mostly physically etchable material, to a much stronger extent than the latter, the advantageous etching speed ratio can be set in that the substrates are additionally raised over the cathode surface.

Abstract: Sintered glass-ceramic substrates containing multi-level, interconnected thick-film circuit patterns of highly conductive metals such as gold, silver or copper are provided which can be fired in air (for gold and silver) or in neutral atmospheres (for copper) at temperatures below the melting points of these metals. This has been made possible by the discovery that finely divided powders of certain glasses described herein sinter to essentially zero porosity at temperatures below 1000.degree. C. while simultaneously maturing to glass-ceramics of low dielectric constant, high flexural strength and low thermal expansivity.

Abstract: A photomask formed of a transparent dielectric substrate, such as glass and quartz based substrates, having a conductive surface adjacent region, which is patterned with sequential overcoatings of a composite chrome oxide layer and a chrome film. The mask comprises a combination of varied reflectivities to provide proper densities for the opaque areas of the mask.

Abstract: An E-beam lithography process for forming via holes in insulating layers, such as quartz, on semiconductor devices. Where quartz is used, an underlayer of an adhesion promoter is used (e.g. KMR resist which is desensitized by heating) followed by overcoating with an E-beam sensitive positive image resist layer of the novolak/diazobenzophenone family. After exposure with an E-beam the development is performed at low temperatures (e.g. 14.degree. C.) with end-point detection to indicate a further degree of overdevelopment, followed by controlled heating to post-bake of the image resist to obtain round and properly tapered via holes.

Abstract: Formation of planar conductor/insulator semiconductor devices utilizing hafnium coated aluminum based metallization with a magnesium oxide mask for dry etching of the metallization and deposition of planar insulation.The hafnium coating is used to protect the aluminum metallization during mask removal, and as a registration enhancer for subsequent electron-beam processing.