Patents Represented by Attorney Heslin Rothenberg Farle & Mesiti P.C.
  • Patent number: 8266802
    Abstract: A cooling apparatus and method of fabrication are provided for facilitating removal of heat from a heat-generating electronic device. The method of fabrication includes: bonding a plurality of thermally conductive pin fins to a surface to be cooled, each pin fin including a stem with a bulb structure on its distal end; depositing material onto the plurality of thermally conductive pin fins to integrally form a jet impingement structure with the pin fins, wherein the distal ends of the plurality of thermally conductive pin fins form part of the jet impingement structure; and controlling the depositing of material onto the distal ends of the pin fins to form a plurality of jet orifices in the jet impingement structure, with the depositing resulting in the plurality of jet orifices automatically self-aligning between the plurality of thermally conductive pin fins.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Levi A. Campbell, Richard C. Chu, Michael J. Ellsworth, Jr., Madhusudan K. Iyengar, Roger R. Schmidt, Robert E. Simons
  • Patent number: 8271743
    Abstract: Automated paging device management is provided for a shared memory partition data processing system. The automated approach includes managing a paging storage pool defined within one or more storage devices for holding logical memory pages external to physical memory managed by a hypervisor of the processing system. The managing includes: responsive to creation of a logical partition within the processing system, automatically defining a logical volume in the paging storage pool for use as a paging device for the new logical partition, the automatically defining occurring absent use of a filesystem, with the resultant paging device being other than a file in a filesystem; and automatically specifying the logical volume as a paging space device for the new logical partition and binding the paging space device to the new logical partition, wherein the logical volume is sized to accommodate a defined maximum memory size of the new logical partition.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bryan M. Logan, James A. Pafumi, Steven E. Royer
  • Patent number: 8243470
    Abstract: An input/output cable port assembly and electromagnetic interference attenuation method are provided. The cable port assembly includes a cable port structure mounted to an electronics rack with an opening for input/output cables to pass therethrough, and multiple bottom ferrite inductor portions and multiple top ferrite inductor portions. The bottom and top ferrite inductor portions include first and second surfaces, respectively. The inductor portions are configured to be stacked within the cable port structure with their first and second surfaces in opposing relation to define at least one ferrite inductor with a central opening defined by the first and second surfaces for input/output cable(s) of the electronics rack to pass. The ferrite inductor attenuates electromagnetic interference resulting from transient or steady state current on the cable(s) passing therethrough.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alma Jaze, Alan H. Knight, John M. Skillman, Kwok M. Soohoo
  • Patent number: 8245214
    Abstract: A system and incorporated method is provided for performing high reliability flash updates using firmware residing in a computing environment. The system comprises a nonvolatile memory having a boot sector and an application sector and a volatile memory in processing communication to update the nonvolatile memory. The volatile memory also includes an implemented algorithm that can temporarily store functions necessary to update the nonvolatile memory via a flash update.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas C. Long, Robert P. Makowicki
  • Patent number: 8243469
    Abstract: An input/output cable port assembly and electromagnetic interference (EMI) attenuation method are provided. The port assembly includes a cable port structure for an electronics rack with an opening for input/output cables to pass therethrough, and a first and a second partition. The first and second partitions couple to the cable port structure and reside within the opening. The first partition includes at least one ferrite inductor portion and the second partition includes at least one second ferrite inductor portion. The partitions are configured to be disposed adjacent to each other as adjoining partitions within the cable port structure, and when disposed as adjoining partitions, the first and second ferrite inductor portions mate and define a ferrite inductor with a central opening for input/output cable(s) of the electronics rack to pass. The ferrite inductor attenuates electromagnetic interference resulting from transient or steady state currents on the cable(s) passing therethrough.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alma Jaze, Alan H. Knight, John M. Skillman, Kwok M. Soohoo
  • Patent number: 8154319
    Abstract: A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first substrate, a first array of nanowires connected to the interface pins of the first interconnect layer, a layer of nanowire junction material over the first array of nanowires, a second array of nanowires over the nanowire junction material, a second interconnect layer having interface pins disposed over the second array of nanowires, the interface pins being connected to the second array of nanowires, and a second substrate, the second substrate including a second CMOS device layer disposed over the second interconnect layer.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: April 10, 2012
    Assignee: The Research Foundation of State University of New York
    Inventor: Wei Wang
  • Patent number: 7921234
    Abstract: In a communications channel coupled to multiple duplicated subsystems, a method, interposer and program product are provided for verifying integrity of subsystem responses. Within the communications channel, a first checksum is calculated with receipt of a first response from a first subsystem responsive to a common request, and a second checksum is calculated for a second response of a second subsystem received responsive to the common request. The first checksum and the second checksum are compared, and if matching, only one of the first response and the second response is forwarded from the communications channel as the response to the common request, with the other of the first response and the second response being discarded by the communications channel.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Vincenzo Condorelli, Thomas J. Dewkett, Michael D. Hocker, Tamas Visegrady