Abstract: A non-integer fractional divider divides a reference clock signal having period P by a non-integer ratio K. The divider includes multiplexers to receive a plurality N of clock signals wherein each clock signal is equally phase shifted by a P/N delay. Incrementers coupled to the multiplexers select first and second clock signals between the N clock signals. Such that the phase shift delay between the two selected clock signals is representative of the non-integer value of K. The selected clock signals are combined to output a divided clock signal. The enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal.
Type:
Grant
Filed:
October 20, 2000
Date of Patent:
June 8, 2004
Assignee:
International Buisness Machines Corporation
Inventors:
Francis Bredin, Bertrand Gabillard, Francois Auguste Roger Meunier