Patents Represented by Law Firm Hickman Beyer & Weaver, LLP
  • Patent number: 5627863
    Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below a threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: May 6, 1997
    Assignee: Amati Communications Corporation
    Inventors: James T. Aslanis, Jacky S. Chow
  • Patent number: 5598120
    Abstract: A digital integrated circuit provided with a dual latch clocked LSSD that includes a master latch coupled to a slave latch such that it operates in at least three operational modes. Preferably the three modes of the dual latch clocked LSSD include a functional mode, a capture mode, and a shift mode. In the functional mode, the dual latch clocked LSSD operates as an edge-triggered flip-flop storage element. In the capture mode, the dual latch clocked LSSD operates as a level sensitive latch storage element controlled by the system clock, one of two scan clock signals, and, preferably, by a test mode input signal. In the shift mode, the dual latch clocked LSSD again operates as a level sensitive latch storage element, but is controlled by a pair of shift clocks. By separating the capture mode from the functional mode, the dual latch clocked LSSD is exceptionally resistant to skew problems in both the capture and the shift modes.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: January 28, 1997
    Assignee: VLSI Technology, Inc.
    Inventor: Stephen A. Yurash
  • Patent number: 5596604
    Abstract: A transmission system using multicarrier modulation applies FECC (forward error correcting code) coding and codeword interleaving differently to input signals from a plurality of different data channels to produce encoded data signals having different reliabilities and different coding delays. Bits of encoded data signals having relatively less delay are allocated to carriers that are subject to relatively more attenuation and/or channel noise, and hence that are allocated fewer bits for transmission in each symbol period, to reduce the effects of impulse noise. The data channels can comprise video, data, and control channels transmitted on an ADSL (asymmetric digital subscriber line) two-wire telephone line.
    Type: Grant
    Filed: August 17, 1993
    Date of Patent: January 21, 1997
    Assignee: Amati Communications Corporation
    Inventors: John M. Cioffi, Po Tong, James T. Aslanis, Antoinette H. Gooch
  • Patent number: 5596697
    Abstract: A method and apparatus are provided for routing information with a pointer-based computer such as a pen-based computer. The routing actions may be faxing, printing, mailing (electronically), and beaming (by infrared light). The routed information may be document or other item produced by or associated with a particular application running on the computer. Routing actions that send items out of the computer system preferably are processed according to the following steps. First one or more menus or windows associated with the application of the document being routed are displayed on a display screen of the computer. At least one of these menus or windows contains a list of routing actions available to the application. The user selects one of these routing actions and, in some cases, provides additional information pertaining to the destination, format, etc. of the document being routed.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: January 21, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Gregg S. Foster, John R. Meier, Stephen P. Capps
  • Patent number: 5573970
    Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: November 12, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Dipankar Pramanik, Subhash R. Nariani
  • Patent number: 5572712
    Abstract: A behavioral synthesis method for making integrated circuits with built-in self-test (BIST). Base specifications describing base functionality and BIST specifications describing BIST functionality are developed. The base specifications are described in a hardware description language (HDL) to create a base HDL which is input into a digital computer system. Utilizing both the base specifications and the BIST specifications, a BIST HDL is created on the digital computer system. A netlist is synthesized on the computer system from both the base HDL and the BIST HDL. Thereafter, a digital integrated circuit is produced as specified by the netlist. An advantage of the present invention is the description of BIST circuitry at the HDL level of abstraction instead of at the netlist level. By automatically generating BIST HDL given BIST specifications and base circuit specifications, a circuit designer is relieved of the complications of gate level manipulations to insert a BIST description into a netlist.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: November 5, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Kamran Jamal
  • Patent number: 5558902
    Abstract: A coating method for detecting the presence of contaminants carried by a liquid that is applied as a coating on a workpiece. A tube guides the liquid along a flow path to the workpiece. A light source illuminates the liquid along the flow path with an optical fiber or other light carrier, and light is scattered by any contaminants present in the liquid. Light scattered by the contaminant particles is more intense than light scattered by the other liquid particles, and this brighter scattered light is detected by a light detector positioned adjacent to the fluid flow path. The coating system is particularly well suited for use in a spin-on coating process that applies a liquid, such as a photoresist material or a dielectric material, to a semiconductor wafer or other workpiece that is secured to a rotating turntable and rotated to receive a coating of the liquid.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 24, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Anthony Sayka, Patricia A. Vargas
  • Patent number: 5557614
    Abstract: A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the flaming information on the input signal and the flaming format.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: September 17, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Lorin H. Sandler, Neal T. Wingen
  • Patent number: 5550877
    Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 27, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Michael R. Waters
  • Patent number: 5546432
    Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 13, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Michael R. Waters