Patents Represented by Law Firm Hickman & Martine, LLP
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Patent number: 5841787Abstract: Disclosed is a loadboard that includes a plurality of channel pins that are arranged on the loadboard. The plurality of channel pins are electrically routed on the loadboard to a receptacle that is configured to receive I/O pins of an integrated circuit chip. The loadboard further includes a programming and test circuit that is integrated on the loadboard, and is coupled to a set of the plurality of channel pins to enable communication with the integrated circuit chip. The programming and test circuit includes a programming sub-circuit for communicating a plurality of voltage levels set by a programming vector to the integrated circuit chip, and a bias sub-circuit for communicating a plurality of bias voltage levels set by the programming vector to the integrated circuit chip.Type: GrantFiled: November 21, 1997Date of Patent: November 24, 1998Assignee: VLSI Technology, Inc.Inventors: Khushwinder S. Warring, David K. Skaare
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Patent number: 5834356Abstract: Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed.Type: GrantFiled: June 27, 1997Date of Patent: November 10, 1998Assignee: VLSI Technology, Inc.Inventors: Subhas Bothra, Dipankar Pramanik, Xi-Wei Lin
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Patent number: 5831385Abstract: A mercury dispensing device is disclosed that includes a mercury dispenser having the formula Ti.sub.x Zr.sub.y Hg.sub.z in which x and y are between 0 and 13, inclusive, the quantity x+y is between 3 and 13, inclusive, and z is 1 or 2; and a promoter that comprises copper, silicon and possibly a third metal selected among the transition elements. A getter material selected among titanium, zirconium, tantalum, niobium, vanadium and mixtures thereof, and alloys of these metals with nickel, iron or aluminum can be included in the device. The mercury dispenser, promoter and optional getter material are provided preferably in the form of powders compressed as a pellet, or contained in a ring-shaped metallic support or rolled on the surfaces of a metallic strip. Also disclosed is a process for introducing mercury into electron tubes by making use of the above-mentioned mercury-dispensing devices.Type: GrantFiled: June 7, 1995Date of Patent: November 3, 1998Assignee: SAES Getters S.p.A.Inventors: Antonio Schiabel, Claudio Boffito
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Patent number: 5830026Abstract: A mercury-dispensing device is disclosed that includes a mercury dispenser having the formula Ti.sub.x Zr.sub.y Hg.sub.z in which x and y are between 0 and 13, inclusive, the quantity x+y is between 3 and 13, inclusive, and z is 1 or 2; and a promoter that comprises copper, silicon and possibly a third metal selected among the transition elements. A getter material selected among titanium, zirconium, tantalum, niobium, vanadium and mixtures thereof, and alloys of these metals with nickel, iron or aluminum can be included in the device. The mercury dispenser, promoter and optional getter material are provided preferably in the form of powders compressed as a pellet, or contained in a ring-shaped metallic support or rolled on the surfaces of a metallic strip. Also disclosed is a process for introducing mercury into electron tubes by making use of the above-mentioned mercury-dispensing devices.Type: GrantFiled: August 26, 1997Date of Patent: November 3, 1998Assignee: SAES Getters S.p.A.Inventors: Antonio Schiabel, Claudio Boffito
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Patent number: 5828870Abstract: A method for controlling clock skew in an integrated circuit which includes a plurality of functional blocks which each contain a control circuit that is in communication with a gated clock includes: a) providing a source clock signal to the control circuit, b) providing a reference clock signal to the control circuit, the reference clock signal being substantially derived from the source clock signal, wherein the reference clock signal has a reference clock phase delay that is greater a phase delay of the gated clock, c) generating a control signal using the reference clock signal and the gated clock, the control signal being arranged to indicate a relationship between the reference clock signal and the gated clock, and d) generating a controlled gated clock using the control signal, wherein the controlled gated clock is generated at least in part by adding a suitable delay to the source clock signal, the controlled gated clock having a controlled gated clock phase delay which is substantially the same as thType: GrantFiled: June 30, 1997Date of Patent: October 27, 1998Assignee: Adaptec, Inc.Inventor: Peter Gunadisastra
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Patent number: 5825308Abstract: A force feedback interface having isotonic and isometric control capability coupled to a host computer that displays a graphical environment such as a GUI. The interface includes a user manipulatable physical object movable in physical space, such as a mouse or puck. A sensor detects the object's movement and an actuator applies output force on the physical object. A mode selector selects isotonic and isometric control modes of the interface from an input device such as a physical button or from an interaction between graphical objects. Isotonic mode provides input to the host computer based on a position of the physical object and updates a position of a cursor, and force sensations can be applied to the physical object based on movement of the cursor. Isometric mode provides input to the host computer based on an input force applied by the user to the physical object, where the input force is determined from a sensed deviation of the physical object in space.Type: GrantFiled: November 26, 1996Date of Patent: October 20, 1998Assignee: Immersion Human Interface CorporationInventor: Louis B. Rosenberg
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Patent number: 5826048Abstract: A Mini-PCI (MPCI) interface, and associated circuits and methods are provided for connecting a Peripheral Component Interconnect (PCI) device to one or more external devices. The MPCI interface, circuits and methods provide for a substantial if not full implementation of a PCI Local Bus without requiring the standard number of pins, traces, or signals. The MPCI interface includes a PCI/MPCI bridge connected between a PCI bus and to up to eight external devices in the form of MPCI devices and linear memory devices. The PCI/MPCI bridge is capable of receiving an incoming PCI transaction and multiplexing some of its signals together to create a corresponding incoming MPCI transaction. This incoming MPCI transaction may then be passed over an MPCI bus, having fewer lines and optimally operating at a higher frequency, the external devices. The process is reversed for outgoing transactions, i.e., the MPCI transactions are de-multiplexed to create PCI transactions.Type: GrantFiled: January 31, 1997Date of Patent: October 20, 1998Assignee: VLSI Technology, Inc.Inventors: Morgan James Dempsey, Rajeev Jayavant
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Patent number: 5825623Abstract: Encapsulated thermally enhanced (TE) and electrically and thermally enhanced (ETE) integrated circuit assemblies that include bulky thermally conductive heat sinks are disclosed. The integrated circuit assemblies are configured to prevent the formation of pinholes and IC package warpage without adding bulk or additional structures. The assemblies are repositioned, through an offset in the bonding fingers of the leadframe, so that the rates of mold flow in the two halves of the mold cavity are substantially balanced. The repositioning of the assemblies also substantially balances the amount of mold material in the mold halves, which prevents warpage in a finished IC package.Type: GrantFiled: December 8, 1995Date of Patent: October 20, 1998Assignee: VLSI Technology, Inc.Inventors: Sang S. Lee, Che-Yuan Chen
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Patent number: 5821558Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.Type: GrantFiled: February 3, 1997Date of Patent: October 13, 1998Assignee: VLSI Technology, Inc.Inventors: Yu-Pin Han, Ying-Tsong Loh, Ivan Sanchez
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Patent number: 5821803Abstract: The present invention teaches a variety of electrical devices and methods for connecting a switch such as a transistor to decrease a voltage drop across an electrical coupling connecting the switch's source with a gate driver regulating operation of the switch, the voltage drop due, at least in part, to a change in current flowing through the switch. Decreasing the voltage drop from the switch's source to the gate driver tends to improve the operational characteristics of the switch. One embodiment of the present invention teaches an electronic device including a switch having a gate, a drain, and a source, and a plurality of source terminals. A gate bias voltage V.sub.gs (the voltage potential from the gate to the source) controls a flow of current through the switch between the drain and the source. The source terminals are each connected to the source by a distinct electrical coupling, each of the electrical couplings having some inductance.Type: GrantFiled: June 19, 1997Date of Patent: October 13, 1998Assignee: Maxim Integrated Products, Inc.Inventor: Bruce D. Moore
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Patent number: 5821920Abstract: An apparatus for interfacing an elongated flexible object with an electrical system. The apparatus includes an object receiving portion and a rotation transducer coupled to the object receiving portion adapted to determine the rotational motion of the elongated flexible object when the object is engaged with the object receiving portion and to provide an electromechanical interface between the object and the electrical system. In a preferred embodiment, the rotation transducer includes an actuator and translational transducer to provide a translational electromechanical interface between the object and the electrical system.Type: GrantFiled: March 28, 1997Date of Patent: October 13, 1998Assignee: Immersion Human Interface CorporationInventors: Louis B. Rosenberg, Ramon Alarcon
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Patent number: 5818532Abstract: Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the video core architecture. The disclosed video decoder core design specifies that at least the following MPEG-2 functions are performed by the hardware: inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge. Other MPEG-2 functions such as motion vector decoding, variable length decoding, and run level decoding are not performed by hardware video cores fabricated in accordance with video core design.Type: GrantFiled: May 3, 1996Date of Patent: October 6, 1998Assignee: LSI Logic CorporationInventors: Srinivasa R. Malladi, Venkat Mattela
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Patent number: 5819093Abstract: A system and method for providing a distributed debugger system for a distributed target computer application are disclosed wherein the programmer/developer of the application can be at one host machine and wherein the application being developed makes use of objects and object implementations which may be located on a different host machine which is unknown to the programmer/developer. The system and method provides solutions to problems which are encountered in trying to debug a new application which is associated with the use of objects in a widely distributed, object oriented, client-server system. In a distributed object environment, requests and replies are made through an Object Request Broker (ORB) that is aware of the locations and status of objects. One architecture which is suitable for implementing such an ORB is provided by the Common Object Request Broker Architecture (CORBA) specification.Type: GrantFiled: March 3, 1995Date of Patent: October 6, 1998Assignee: Sun Microsystems, Inc.Inventors: Andrew E. Davidson, Jon A. Masamitsu
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Patent number: 5815675Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.Type: GrantFiled: June 13, 1996Date of Patent: September 29, 1998Assignee: VLSI Technology, Inc.Inventors: James C. Steele, Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli, David Cassetti, Rodney Pesavento, Nick Richardson
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Patent number: 5815206Abstract: Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.Type: GrantFiled: May 3, 1996Date of Patent: September 29, 1998Assignee: LSI Logic CorporationInventors: Srinivasa R. Malladi, Marc A. Miller, Kwok K. Chau
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Patent number: 5804744Abstract: A low contamination bottle for sampling, storing, and transporting of chemical samples includes a bottle portion defining an internal volume and having a threaded neck, and a cap portion provided with threads that engage the threaded neck of the bottle to provide a fluid-tight seal between the internal volume of the bottle and the ambient environment. The bottle has a flexible sidewall portion that permits the reduction of the internal volume to allow a liquid sample to be drawn into the bottle portion by a suction or vacuum process. Both the bottle portion and the cap portion are made from a material selected from the chemical resistant group consisting essentially of hydrocarbon polymers and fluorocarbon polymers, where the material generates less then 1 ppb of metal contaminants and 1 ppm of leachable anionic and organic contaminants. The flexible sidewall portion of the bottle portion has a minimum thickness of 0.Type: GrantFiled: September 30, 1996Date of Patent: September 8, 1998Assignee: ChemtraceInventors: Samantha S. H. Tan, Dianne M. Dougherty
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Patent number: 5804340Abstract: A method of inspecting a photomask for use in photolithography which accounts for the rounding of corners of features that occurs during manufacture of the photomask. A data tape used in the preparation of the photomask is first provided. An inspection tape is then prepared by modifying the data on the data tape to account for rounding of the features during preparation of the photomask. Finally, an inspection device is used to compare features on the photomask to data on the inspection tape corresponding to such features.Type: GrantFiled: December 23, 1996Date of Patent: September 8, 1998Assignee: LSI Logic CorporationInventors: Mario Garza, Keith K. Chao
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Patent number: 5803451Abstract: A skill-based game including multiple score indicators is disclosed. The skill-based game preferably involves rolling a playing piece down a playing surface towards targets, and allowing the user to use the targets to manipulate multiple score indicators, so as to use one's skill to obtain a winning combination. In a preferred embodiment, the playing piece is a ball and the multiple score indicators are mechanically rotated dice. Progressive scoring can also be provided. The invention attracts players and retains their interest so that they tend to repeatedly use the game.Type: GrantFiled: September 17, 1996Date of Patent: September 8, 1998Assignee: RLT Acquisition, Inc.Inventors: Matthew F. Kelly, Bryan M. Kelly
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Patent number: 5804502Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.Type: GrantFiled: January 16, 1997Date of Patent: September 8, 1998Assignee: VLSI Technology, Inc.Inventors: Calvin T. Gabriel, Dipankar Pramanik, Xi-Wei Lin
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Patent number: 5805137Abstract: A family of controllers incorporate multiple force/touch sensitive input elements to provide intuitive input in up to six degrees of freedom, including position and rotation, in either a Cartesian, cylindrical or spherical coordinate system. Six dimensions of input can be generated without requiring movement of the controller, which provides a controller suitable for controlling cursors and display objects in an interactive computer system and for equipment such as heavy cranes and fork lift trucks. Positional information is obtained either by use of a "pushing" or "dragging" metaphor. Rotational information is provided by either a "pushing," "twisting," or "gesture" metaphor. In certain embodiments, the same sensor is used for both positional and rotational inputs, and the two are differentiated by the magnitude of the force applied to the sensor.Type: GrantFiled: May 5, 1994Date of Patent: September 8, 1998Assignee: ITU Research, Inc.Inventor: Taizo Yasutake