Abstract: A method and computer program product for receiving a slot request, from a second respondent having a second seniority level, for an original event slot that was previously reserved by a first respondent having a first seniority level. The second seniority level is compared to the first seniority level. If the second seniority level exceeds the first seniority level: the reservation of the original event slot by the first respondent is cancelled, and the event slot request for the original event slot by the second respondent is accepted.

Abstract: A method and computer program product for leveraging the creation context of a tag includes creating one or more tags, each of the one or more tags associated with a respective piece of content. A creation context is associated with each of the one or more tags. The one or more tags are searched based upon, at least in part, the creation context.

Abstract: Embodiments relate to pushing data to mobile devices more efficiently. In a first embodiment, a computer-implemented method receives pushed data on a mobile device. The method includes: (a) recording, at a memory of the mobile device, information describing activity occurring on the mobile device during a first time period; (b) sending, from the mobile device to a server, data indicating the first time period and activity data indicating whether the mobile device was active during the first time period; and (c) during a second time period occurring after the recording (a) and sending (b), receiving application data pushed to the mobile device at a first rate determined based at least in part on the activity data sent to the server in (b), wherein the second time period is determined by the server based at least in part on the data indicating the first time period.

Abstract: A method, computer program product, and system for routing computer network traffic include associating, on a routing device, a unique identifier with at least one application server running an application. Network traffic that includes the unique identifier and an intended network address may be received. In response to receiving the network traffic at least one of the application servers associated with the unique identifier may be identified. The network traffic may be forwarded to at least one of the application servers associated with the unique identifier.

Abstract: One or more data structures are received by a computing device, wherein the one or more data structures include at least one or more user credentials. The one or more user credentials are normalized by the computing device to generate a first graph. One or more nodes of the first graph and one or more nodes of at least a second graph are analyzed by the computing device, wherein analyzing includes at least identifying a logical correlation between the one or more nodes of the first graph and the one or more nodes of at least the second graph. A third graph is generated by the computing device based, at least in part, upon the analysis of the one or more nodes of the first graph and the one or more nodes of at least the second graph. An output data structure is generated by the computing device based, at least in part, upon the third graph.

Abstract: Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.

Abstract: Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.

Abstract: Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power state switchable between a power-on state and a power-off state. The logic design is traversed to analyze driver and load logic of each of the primary inputs to the switchable power domain to identify any pure pass-through nets each of which has no driver and no load logic in the switchable power domain.

Abstract: Method and apparatus for implementing a task-based interface in a logic verification system is described. In some examples, a task server and a context memory are implemented in a hardware accelerator for a task. The task server is configured for communication with the logic design. A task stub configured for execution by a computer for the task is generated. Calls to the task are received from a test bench in the computer at the task stub. Remote procedure call (RPC) channels are established in response to the calls. Values of input arguments for the calls are transferred to the context memory through the RPC channels. Execution of threads of the task in the task server is triggered using the values of the input arguments in the context memory as parametric input.

Abstract: In one embodiment, a method comprises partitioning a circuit description into a plurality of simulateable partitions. The partitioning is independent of a hierarchy specified in the circuit definition. The method also comprises sorting the plurality of simulateable partitions into one or more groups, wherein each simulateable partition included in a given group is equivalent to each other partition in the given group. Further, the method comprises simulating a first simulateable partition in the given group responsive to one or more input stimuli to the first simulateable partition. For each other simulateable partition in the given group that has approximately the same input stimuli as the first simulateable partition, the method still further comprises using a result of simulating the first simulateable partition as a result of the other simulateable partition.

Abstract: A ballast comprising a first input terminal, a second input terminal, a switch circuit, and a plurality of lamp sets is provided. The switch circuit comprises a first switch and a second switch connected with the first one. The switches are connected with the first and second input terminals respectively. The lamp sets are connected in parallel with each other and have an arrangement sequence. Each of the lamp sets is coupled to the first and second switches and comprises a first lamp having a first filament. The filaments are connected in series according to the arrangement order so that at least one junction is formed in the at least one connection point. The first one of the first filaments is coupled to the first switch. The last one of the first filaments is coupled to the second switch. Thereby, the ballast can be implemented by less internal connection terminals and leads.

Abstract: A method and computer program product for receiving an indication of a meeting being scheduled between a plurality of attendees. At least one of the attendees is designated a moderator of the meeting. The actions of the designated moderator are monitored to determine if the designated moderator is capable of performing one or more moderator responsibilities associated with being the designated moderator. If it is determined that the designated moderator is incapable of performing the one or more moderator responsibilities, an alternate moderator chosen from the plurality of attendees is designated.

Abstract: A method and system of detecting vulnerabilities in source code. Source code is parsed into an intermediate representation. Models (e.g., in the form of lattices) are derived for the variables in the code and for the variables and/or expressions used in conjunction with routine calls. The models are then analyzed in conjunction with pre-specified rules about the routines to determine if the routine call posses one or more of pre-selected vulnerabilities.

Abstract: A wind turbine wiring enclosure cabinet is provided having a housing and an electrical circuit connection means. The housing has a top surface, a bottom surface, and a sidewall in contact with the top surface, the top surface having a plurality of apertures formed therein. The housing has an interior, and the sidewall has at least one door accessing the interior. The electrical circuit connection means includes a plurality of non-conductive vertical members, and a plurality of conductive elements having connected thereto a plurality of connector retention means. Each connector retention means has a slot formed therein for insertion therein of a lay-in lug assembly. Each non-conductive vertical member has two sidewalls with an intermediate wall connected to each of the two sidewalls. The apertures formed in the top surface are arranged in a plurality of groups, as are the apertures formed in the bottom surface.