Abstract: A method for providing color correction to a color marking engine for halftone and contone images includes the step of first generating a test pattern. This test pattern has a plurality of discrete images disposed thereon with the discrete images having characteristics that are correlated with parameters of the print job. In one mode, they relate to halftone images that have differing densities of dots, each less than 100% density. The images are correlated to different bit values for the same densities such that the maximum density value for the pixel is offset for different images. A user then views the different images and determine which one is closest to a true gray and then selects the offset bit value for that image as the marking engine offset. This can then be applied to that particular marking engine. This can be utilized for a plurality of marking engines (651) with a single RIP (650).

Abstract: A load center monitor (10) is disclosed for monitoring and analyzing data gathered by electronic circuit breakers (40) in a power distribution system and communicated to the load center monitor (10) via a network (26) coupling the load center monitor (10) and the circuit breakers (40) together. The load center monitor (10) includes a first communication port (24) for communicating with the circuit breakers (40), a second communication port (20 or 22) for communicating with an external device and third communication port (28) for providing diagnostic information. The load center monitor (10) further includes audible (30) and visible (34) annunciators for providing alarm or status indications. A processor (76), coupled to the communication ports and to a memory (70) having a real-time clock for time stamping data provides monitoring, control, analysis and data generating capability in the load center monitor (10).

Abstract: A system including a load center monitor (10) connected to a plurality of digitally enhanced circuit breakers (40) by a communication bus (26) forms a network of reconfigurable circuit breakers which provides advanced monitoring and control of an electrical power distribution system. A user port (20) and a service port (22) provide a communication interface with an external computer. Visual indicators (34) and an audible alarm (30) provide for alerting persons to certain conditions in the system. Buttons are provided for CLEAR (38), RESET (36), and TEST functions, and a diagnostic port (24) is also provided. The load center monitor (10) is operable to monitor the operation of the circuit breakers (40) and download information therefrom for storage in the load center monitor (10) as in the form of historical data.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

Abstract: A predictive network is disclosed for operating in a runtime mode and in a training mode. The network includes a preprocessor (34') for preprocessing input data in accordance with parameters stored in a storage device (14') for output as preprocessed data to a delay device (36'). The delay device (36') provides a predetermined amount of delay as defined by predetermined delay settings in a storage device (18). The delayed data is input to a system model (26') which is operable in a training mode or a runtime mode. In the training mode, training data is stored in a data file (10) and retrieved therefrom for preprocessing and delay and then input to the system model (26'). Model parameters are learned and then stored in the storage device (22). During the training mode, the preprocess parameters are defined and stored in a storage device (14) in a particular sequence and delay settings are determined in the storage device (18).