Patents Represented by Attorney Hulsey, Grether + Fortkort, LLP
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Patent number: 6862971Abstract: A ballistic protection composite shield is disclosed, with improved next-to-skin properties, and improved flexibility. Needlepunching technology permits the manufacture of the wear layer using any type of fiber, and advantageously allows distinct layering, fiber blending, compressibility, controlled fiber orientation, and increases z-directional strength. Needlepunching the nonwoven wear layer to the woven antiballistic layer mechanically interconnects the two layers, eliminating the need for an adhesive bond and increasing the flexibility of the shield. An abrasion resistant strike layer, such as leather, increases the life of the shield.Type: GrantFiled: December 17, 2002Date of Patent: March 8, 2005Assignee: Texas Tech UniversityInventor: Seshadri S. Ramkumar
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Patent number: 6801612Abstract: Provided is a system and method for consolidating telephone calls from more than one individual to a single, remote conference call provider through a telephone switch such that the multiple calls utilize a single telephone connection between the individuals' location and the conference call provider. A private branch exchange (PBX) or other type of switch detects attempts by multiple local callers to reach a designated conference call number and multiplexes those calls. In one embodiment, at least one of the conference call participants is coupled to the switch via a network, such as the Internet, using an Internet protocol (IP) telephone connection.Type: GrantFiled: November 21, 2002Date of Patent: October 5, 2004Assignee: International Business Machines CorporationInventors: Jerry W. Malcolm, Cornell G. Wright, Jr.
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Patent number: 6796482Abstract: A solder flux composition (19) is provided which comprises active ingredients and a carrier. The solder flux composition undergoes a phase separation during solder reflow to form at least a first phase (21) and a second phase (23), such that the active ingredients are disposed primarily in the first phase and the carrier is disposed primarily in the second phase. The use of this solder flux composition is found to reduce solder migration, during solder reflow, that can result in bridging in ball grid arrays and other such devices.Type: GrantFiled: October 31, 2002Date of Patent: September 28, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Li Ann Wetz, Treliant Fang
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Patent number: 6794272Abstract: A method for manufacturing integrated circuits uses an atmospheric magnetic mirror plasma etching apparatus to thin a semiconductor wafer. In addition the process may, while thinning, both segregate and expose through-die vias for an integrated circuit chip. To segregate, the wafer may be partially diced. Then, the wafer may be tape laminated. Next, the backside of the wafer may be etched. As the backside material is removed, the partial dicing and through-die vias may be exposed. As such, the method reduced handling steps and increases yield. Furthermore, the method may be used in association with wafer level processing and flip chip with bump manufacturing.Type: GrantFiled: March 18, 2003Date of Patent: September 21, 2004Assignee: iFire Technologies, Inc.Inventors: Terry R. Turner, James D. Spain, Richard M. Banks
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Patent number: 6780751Abstract: A method for plating solder is provided. In accordance with the method, a die having a seed metallization thereon is provided. The seed metallization is microetched (85) with a solution comprising an acid and an oxidizer, thereby forming an etched seed metallization. An under bump metallization (UBM) is then electroplated (87) onto the etched seed metallization, and a lead-free solder composition, such as SnCu, is electroplated (91) onto the UBM. A method for reflowing solder is also provided, which may be used in conjunction with the method for plating solder. In accordance with this later method, the substrate is subjected to a seed metallization etch (137), followed by a microetch (141). A solder flux is then dispensed onto the substrate (147) and the solder is reflowed (149).Type: GrantFiled: October 9, 2002Date of Patent: August 24, 2004Assignee: Freescale Semiconductor, Inc.Inventor: Owen Fay
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Patent number: 6770506Abstract: A method for creating a MEMS structure (100) is provided. In accordance with the method, an article is provided comprising a substrate (101), a sacrificial layer (103) and a semiconductor layer (105), wherein the sacrificial layer comprises a first material such as silicon oxide. A MEMS structure is then formed in the semiconductor layer. The structure has first (107) and second (109) elements which have an exposed portion of the sacrificial layer (103) disposed between them. The first element is then released from the substrate (101) by contacting the exposed portion of the sacrificial layer (103) with a first etchant, typically by way of one or more trenches (119), after which the first element is reattached to the substrate (101) with a second material (131). The first element is then released from the substrate (101) by contacting the second material (131) with a second etchant.Type: GrantFiled: December 23, 2002Date of Patent: August 3, 2004Assignee: Motorola, Inc.Inventor: Bishnu Gogoi
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Patent number: 6770569Abstract: A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.Type: GrantFiled: August 1, 2002Date of Patent: August 3, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Juergen A. Foerstner, Steven M. Smith, Raymond Mervin Roop
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Patent number: 6756320Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.Type: GrantFiled: January 18, 2002Date of Patent: June 29, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Matthias Passlack, Nicholas William Medendorp, Jr.
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Controller architecture and strategy for small discontiguous accesses to high-density memory devices
Patent number: 6738874Abstract: A RAM device including a memory and a memory controller. The memory controller can be configured to buffer incoming requests, prioritize the requests into a final order, and submit the requests to the memory in the final order. The final order, as needed, is selected to maximize overlap of incoming requests' timing cycles.Type: GrantFiled: February 16, 2002Date of Patent: May 18, 2004Assignee: Layer N Networks, Inc.Inventor: Leslie Zsohar