Abstract: A lightweight structural concrete with screw-ability and nail-ability similar to wood is composed of a non-structural and ultra lightweight aggregate such as expanded perlite or a combination of expanded perlite and polystyrene beads of a particular size distribution and volume amount, entrained air cells of another specific size distribution and volume amount, and dense cementitious composition of a cement binder, a fine grade structural filler no larger than concrete sand grade, a pozzolan, and optional micro-fibers for reinforcement. This structural concrete matrix is optimized to hold 13 gauge T-nails and bugle head wood screws with thread ranging from 8 to 11 threads per inch and diameter of 0.10? to 0.137?. The resulting concrete will have consistent screw-ability and nail-ability similar to that of wood.

Abstract: A lightweight cementitious panel/tile is provided with increased bending stiffness and less weight than conventional construction panels. The cementitious panel is constructed of a cementitious surface (which may be reinforced with wood fiber or other materials) supported by an integrated stiffener grid on the underside to absorb stresses and loads.

Abstract: A lightweight structural concrete with screw-ability and nail-ability similar to wood is composed of non-structural and ultra lightweight aggregate such as expanded perlite of a particular size distribution and amount, entrained air cells of another specific size distribution and amount, and dense cementitious composition of a cement binder, a fine grade structural filler no larger than masonry sand grade, a pozzolan, and optional micro-fibers for reinforcement. This structural concrete matrix is optimized to hold 13 gauge T-nails and bugle head wood screws with thread ranging from 8 to 11 threads per inch and diameter of 0.10? to 0.137?. The resulting concrete will have consistent screw-ability and nail-ability similar that of wood.

Abstract: An advanced traffic shaper is provided for shaping real-time traffic in an IP-based network while simultaneously providing keep-alive bandwidth for best-effort traffic. The traffic shaper comprises a packet classifier coupled to receive an incoming packet from the network and to classify the incoming packet as one of a real-time packet and a best-effort packet; a packet discarding block coupled to perform traffic shaping of the incoming packet from the packet classifier and discard the incoming packet in accordance with traffic shaping parameters; connection queues coupled to temporary store real-time packets and best-effort packets from the packet discarding block, respectively; and a packet scheduling block coupled to send the real-time and best-effort packets from the connection queues to an outgoing device in accordance with the traffic shaping parameters.

Abstract: A computer system having multiple graphics controllers configured to share graphics and video functions, including each executing a portion of a single block transform “BLT” operation in parallel to transfer a block of pixel data from a source to a destination on a graphics surface; and multiple local memories connected to the graphics controllers and configured to store pixel data of a source in a designated pattern allocated to different graphics controllers, wherein each includes a scratch pad for storing, upon request to execute a single BLT operation, all pixel data of the source that are in regions controlled by another graphics controller and copied from the other local memory.

Abstract: A drum memory controller for controlling random access write and sequential read operations of a drum memory in a communications system. Such drum memory controller (220) may comprise a drum memory (224) having a predetermined number of rows and rings forming a plurality of memory locations arranged in a sequential time order; a random access write address generator (222) which generates write addresses using a respective time tag of incoming data for writing data into memory locations of the drum memory (224) in a random access time order; and a sequential reader (226) which generates read addresses at a constant rate for reading out data stored in the memory locations of the drum memory (224) across each row and then sequencing up in rows in a sequential time order.