Abstract: A charge pump (10) uses Schottky diodes (12) coupled to clock signals (o.sub.1 and o.sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).

Abstract: An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

Abstract: An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Abstract: A new semiconductor controlled rectifier which may be used to provide on-chip protection against ESD stress applied at the input, output, power supply pins or between any arbitrary pair of pins of an integrated circuit is disclosed. The structure which has the lowest breakdown voltage for a given technology is incorporated into the SCR enabling a SCR trigger voltage determined by the lowest breakdown-structure.

Abstract: A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all "1"s, all "0"s, or alternating "1"s and "0"s) is stored (block 10) in each memory cell of the circuit under test. The power to each of the cells is then lowered (block 12) to a selected voltage level which is below the static holding voltage. After a selected time period, the power to each of the cells is restored (block 14) and the logical state present in each cell is compared (block 16) with the initially stored logical state to determine if any of the cells have switched to another logical state. This procedure may be repeated (blocks 18-26) a number of times.

Abstract: A power MOSFET device formed in a face of a semiconductor layer of a first conductivity type is provided. A first, second and third source region of a second conductivity type are formed in the face of the semiconductor layer within a moat and adjacent to its edges. A source conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first, second and third source regions at a plurality of locations. A first and second drain region of a second conductivity type is also formed in the face of the semiconductor layer disposed spaced from and between the first and second source regions and the second and third source regions, respectively. A drain conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first and second drain regions at a plurality of locations.

Abstract: A resistor circuit (and structure) 10 is disclosed herein. A first resistor 14 has a first temperature coefficient of resistance and is coupled to a second resistor 16 which has a second temperature coefficient of resistance, typically opposite to the first temperature coefficient of resistance. The resistors 14 and 16 are coupled together (e.g., in series or in parallel) to create a total resistor with a predetermined (e.g., substantially zero) temperature coefficient of resistance.

Abstract: A gate array base cell (100) performs logic and memory cell functions and comprises a first P-channel transistor (M1) for performing logic functions and having a first predetermined transconductance area and a second P-channel transistor (M5) for performing memory cell functions and having a second predetermined transconductance area. The second transconductance area is smaller than said first predetermined transconductance area. The gate array base cell (100) has programmable connections to first P-channel transistor (M1) and second P-channel transistor (M5) for selectively performing memory cell functions and logic functions. The gate array base cell (100) may be connected to operate as a memory cell with logic functions or separately as a memory cell or a logic gate array, such as a two-input NAND gate (128).

Abstract: A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all "1"s, all "0"s, or alternating "1"s and "0 38 s) is stored (block 10) in each memory cell of the circuit under test. The power to-each of the cells is then lowered (block 12) to a selected voltage level which is below the static holding voltage, but greater than zero volts. The voltage level may have been previously determined. After a selected time period (which may also have been previously determined), the power to each of the cells is restored (block 14) and the logical state present in each cell is compared (block 16) with the initially stored logical state to determine if any of the cells have switched to another logical state. This procedure may be repeated (blocks 18-26) a number of times. Other systems and methods are also disclosed.

Abstract: An improved I.sub.CCQ test method uses illumination of the integrated circuit to generate photo-induced currents and diode effects in order to detect types of circuits faults not otherwise detectable using conventional I.sub.CCQ testing methods.

Abstract: A responder unit (12) located in spaced relation with respect to an interrogator unit (10) is described. The responder unit (12) has a responder unit receiver (130) for receiving at least one RF interrogation pulse, a responder unit memory (168) containing a potentially unique responder unit group address, a responder unit controller (202) operably connected to the memory (168) for comparing the potentially unique responder unit group address to the Group Address, and a responder unit transmitter (130) for transmitting a RF response when the potentially unique responder unit group address matches the Group Address.

Abstract: Apparatus and method for producing a flexible antenna suitable to be incorporated in a badge or similar object. The antenna comprises electrical windings (28, 38) surrounding a flexible antenna core (26, 36). The antenna core (26, 36) is of a material having a high quality factor formed of a plurality of mutually insulated, longitudinally extending chains of magnetic soft material of high .mu.. According to one embodiment, a powder of small particles of a magnetic soft material of high .mu. is mixed with a synthetic resin so that a high saturation of magnetic material in the mixture is formed in a vacuum. The mixture is cured in a strong magnetic field so that the particles form chains (18A, 18B, 18C) of the particle parallel to the applied magnetic field.

Abstract: A multi-switch processing methodology and a multi-channel time-division plasma chopping device (10) for in-situ plasma-assisted semiconductor wafer processing associated with a plasma and/or photochemical processing equipment. The device (10) comprises a main transfer channel (72) associated with the processing reactor for transferring process gas and activated plasma mixtures into the reactor. A plurality of gas discharge channels (18, 22, 26, and 30) associate with the main transfer channel (72) for independently directing various gases and activated plasma combinations to main transfer channel (72). Process excitation sources (16, 20, 24 and 28) associate with at least one of said gas discharge or activation channels to independently and selectively activate process gases and to control gas activation and flow from the discharge channels to the main transfer channel (72).

Abstract: A system 20 for measuring the sheet resistance of a conductive layer on the top surface of a semiconductor wafer 22 is disclosed herein. In one embodiment, the system includes a chuck 30 electrically coupled to the backside surface of the wafer 22. The chuck 30 is capable of supporting the wafer 22 electrostatically. A signal source 40 provides an excitation signal to the wafer 22 and circuitry for monitoring an induced signal is provided. The sheet resistance on the top surface of the wafer 22 is determined from the measurements of the excitation and induced electrical signals. Other systems and methods are also disclosed.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: A pulse generator circuit 20 is disclosed herein. An asymmetric delay element 22 is coupled to one of the inputs of a logic element 24, such as a NAND gate. For the asymmetric delay 22, the time to propagate a transition from a high level to a low level is different then the time to propagate a transition from a low level to a high level. The input of the asymmetric delay element 22 is coupled to another of the inputs of the logic gate 24. The pulse generator circuit 20 of the present invention generates a pulse at its output OUT when a signal applied to its input IN transitions from a first signal level to a second signal level.

Abstract: According to the invention, an electrically-erasable, electrically programmable read-only memory cell is formed at the face of a semiconductor layer 321 of a first conductivity type. A source region 311 and a drain region 312 are formed at the face of semiconductor layer 321 to be of a second conductivity type opposite the first conductivity type. Source region 311 and drain region 312 are spaced by a channel 313. A tunneling oxide window 327 is formed adjacent source region 311. A floating gate 314 is formed insulatively adjacent the entire length of channel 313 between source region 311 and drain region 312. Floating gate 314 is also formed directly adjacent tunneling oxide window 327. A control gate 315 is disposed 15 insulatively adjacent floating gate 314.

Abstract: An apparatus and method for maintaining variable data in a non-volatile electronic memory device comprises a shifter array (106) which provides a shifter value to shifter register (104). Shifter register (104) uses 8-bit column decoder (110) to specify which of a plurality of overlapping storage units in array (94) will store variable data provided from register (92). Address register (112) specifies to row decoder (116) which of two rows in shifter array (106), pointer array (118) and array (94) will be accessed by read and write operations. Pointer array (118) stores an index specifying which of the two rows contains the most recently updated variable data. Shifter register (104) uses 8-bit column decoder (108) to specify which of a plurality of adjacent storage units in pointer array (118) will store the index. OR gate (98) specifies when to replace an overlapping storage unit in array (94) and an adjacent storage unit in pointer array (118).