Abstract: A method for reducing the transient response time of a voltage regulator when the load attached to it is entering or exiting a lower power consumption level by changing the bandwidth of the voltage regulator without compromising its stability, and a bandwidth regulator for implementing such a method are disclosed, wherein the bandwidth of the voltage regulator is changed based on a signal sent by a control device when it senses that the component is about to change power consumption levels.

Abstract: A circuit for driving a motor used to control the HVAC blend door in an automobile is disclosed. The circuit includes an amplifier circuit, an motor, and a three state driver circuit. The driver circut includes three NPN bipolar transistors and two PNP bipolar transistors configured such that the output of the three state driver circuit is turned off if the input is at a intermediate voltage. The output of the three state driver circuit is at a high voltage if the input is at a low voltage. Conversely, the output of the three state driver circuit is at low voltage when the input is at a high voltage.

Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.

Abstract: A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable inputs, are used to enable test operation mode and to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the memory cells. Contemporaneously are also exercised entire paths of buffers. The silicon wafer is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test for ionic contamination, trap sites and weak oxides a plurality of integrated circuits on the same wafer in a short time, requiring only a limited number of test signals.

Abstract: A redundancy structure having fewer pass gates in the redundant decoder for quicker access to a redundant columns and a reduction in the complexity of the redundancy structure.

Abstract: A stator coil driver circuit for a brushless DC motor, with an improved current mirror, is disclosed. The improved current mirror has a first transistor which conducts current and a second transistor configured to mirror the current of the first transistor. Additionally, the improved mirror circuit includes a unity gain amplifier connected in between the gates of the first and second transistor. The effect of the unity gain transistor is to provide for a faster turn-off of the second transistor and reduce oscillation of the circuit.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.

Abstract: A system and method are provided for disabling the edge transition detection circuit during the flash clear cycle, thereby preventing the generation of an edge transition detection pulse. In a preferred embodiment of the invention, the edge transition detection circuit is connected to the flash clear complement circuitry through a logic gate. During the flash clear cycle, flash clear true, FC.sub.T, is pulled high, flash clear complement, FC.sub.c, is pulled low and inverted to drive a portion of the ETD circuitry high, thereby preventing generation of an ETD pulse during the flash clear cycle.