Patents Represented by Attorney Ishimaru & Associates LLP
  • Patent number: 8269324
    Abstract: An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Arnel Senosa Trasporto, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 8269356
    Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rajendra D. Pendse, Byung Joon Han, Hun Teak Lee
  • Patent number: 8270176
    Abstract: An integrated circuit package system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 8264091
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: September 11, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 8265421
    Abstract: A video system includes: analyzing video data, having a block; performing a transition change detection for determining a spatial intensity transition within the block; performing a block-wise similarity measurement on the block in the video data for identifying a blocking artifact; and filtering with a two dimensional cross filter every pixel in the block for removing the blocking artifact.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: September 11, 2012
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Ximin Zhang, Ming-Chang Liu
  • Patent number: 8258612
    Abstract: A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: September 4, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Heap Hoe Kuan, Rui Huang, Yaojian Lin, Seng Guan Chow
  • Patent number: 8258614
    Abstract: An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Abelardo Jr. Hadap Advincula, Lionel Chien Hui Tay
  • Patent number: 8256660
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: September 4, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Patent number: 8258609
    Abstract: An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing to an inner body bottom side of the inner lead, connecting the integrated circuit die and the inner lead, and encapsulating the inner lead having the lead support thereover and the inner lead exposed.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jose Alvin Caparas, Arnel Trasporto
  • Patent number: 8252634
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing inwardly converging leadfingers having continuously decreasing widths along lengths thereof to inward ends thereof; electrically connecting an integrated circuit device on the leadfingers only on portions of the continuously decreasing widths; and encapsulating the integrated circuit device and the leadfingers with an encapsulation.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 28, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Jose Alvin Caparas, Lionel Chien Hui Tay
  • Patent number: 8252615
    Abstract: An integrated circuit package system that includes: providing a support structure including an integrated circuit and an electrical contact adjacent thereto; providing a first mold having a first cavity with a projection and a recess for collecting flash; engaging the first mold on the support structure with the first cavity over at least a portion of the integrated circuit and the projection and the recess between the at least a portion of the integrated circuit and the electrical contact; and injecting encapsulation material into the first cavity.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 28, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Patent number: 8247894
    Abstract: An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched within the recess; and connecting the top integrated circuit package system and the stackable integrated circuit package system.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: August 21, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: In Sang Yoon, HanGil Shin, Jae Han Chung, DeokKyung Yang
  • Patent number: 8247893
    Abstract: A mountable integrated circuit package system comprising: mounting a first integrated circuit device over a package carrier; mounting an interposer including a central aperture over the package carrier, an intra-stack interconnect connected between the interposer and the package carrier, and the first integrated circuit device within the central aperture; and forming an intra-stack encapsulation over the package carrier and surrounding the interposer.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: YoungJoon Kim, Soo-San Park
  • Patent number: 8241965
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 14, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Flynn Carson, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Patent number: 8242607
    Abstract: A method of manufacture of an integrated circuit package system comprises: providing a first integrated circuit die; attaching a second integrated circuit die over the first integrated circuit die and offset from the first integrated circuit die in substantially one dimension; forming an interdie layer over the second integrated circuit die; attaching a third integrated circuit die over the interdie layer and substantially aligned to the second integrated circuit die; and attaching a fourth integrated circuit die over the third integrated circuit die and offset from the third integrated circuit die in substantially the same magnitude and substantially the opposite direction as the second integrated circuit die to the first integrated circuit die.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: August 14, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: Chee Keong Chin
  • Patent number: 8241955
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect over the base circuit assembly, the inner interconnect on the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and the outer interconnect.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: August 14, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Jong-Woo Ha
  • Patent number: 8236607
    Abstract: A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a base component to the substrate by a first interconnect; attaching a stack component connected by a second interconnect to the substrate and partially over the base component, the second interconnect different from the first interconnect; molding an encapsulation over the base component, the first interconnect, the stack component, and the second interconnect; and removing the substrate to partially expose the first interconnect and the second interconnect from the encapsulation.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 7, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 8232658
    Abstract: A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: July 31, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
  • Patent number: 8232141
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: July 31, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, JoHyun Bae, Junghoon Shin
  • Patent number: 8232877
    Abstract: A method of operation of a navigation system includes: receiving a context boundary; receiving a boundary criteria for the context boundary; identifying a personal physical characteristic for monitoring a monitored person; detecting a personal noncompliance to the boundary criteria based on a discrepancy of the personal physical characteristic; and generating an alert based on the personal noncompliance for displaying on a device.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 31, 2012
    Assignee: Telenav, Inc.
    Inventor: Aliasgar Mumtaz Husain