Patents Represented by Attorney, Agent or Law Firm Isis E. Caulder
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Patent number: 6815673Abstract: A method and apparatus for the analysis of a narrow range of fragment ions by application of a notched broadband waveform during ion accumulation within a quadrupole collision cell operated as a linear ion trap. The fragment ions are formed via the axial acceleration and collision activated dissociation of mass resolved precursor ions. A narrow band of frequencies is purposefully omitted from the spectrum, so that the secular frequency of a particular fragment ion will fall within this notch of absent frequencies and as a result will not experience resonant excitation and are retained in the linear ion trap. Simultaneously, all other ions are lost either through neutralization when they strike electrodes or through (additional) collision activated dissociation. Accordingly, a particular mass or range of masses, whose secular frequencies fall within the notch of absent frequencies in the notched broadband waveform, may be selectively accumulated during the collision activated dissociation event.Type: GrantFiled: December 19, 2002Date of Patent: November 9, 2004Assignee: MDS Inc.Inventors: Jeffry B. Plomley, Frank A. Londry
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Patent number: 6751439Abstract: An interactive on-line music training system for teaching music to students comprises a Student Station, a Teacher Station, and an Administrative Web Server connected over a communications network. The Student Station includes a computer which is integrated with a MIDI device (e.g. MIDI keyboard). The Administrative Web Server maintains a database for storing data related to the Student's performance. The Student uses the MIDI device to interact with the music course. As the Student traverses the music course, lessons and activities as well as the applicable MIDI files are downloaded from the Administrative Web Server to the Student Station's computer. The Student's responses to exercises are stored as a MIDI file on the student computer. Upon completion of a lesson, an activity is presented to the Student.Type: GrantFiled: May 22, 2001Date of Patent: June 15, 2004Assignee: Great West Music (1987) Ltd.Inventors: Deanna L. Tice, Susan L. Douglas, Andrew L. Parsons, Stuart D. McClune, Alain J. P. Lussier, Ian Jonathan Perkins, Timothy M. Nachtigall, Michael L. Munro, Trevor C. Sawler, Michael J. Savoy
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Patent number: 6733324Abstract: A coaxial heat sink connector for providing a thermal path from the conductors associated with a coaxial cable connector to a heat sink includes a center conductor, an outer conductor, an insulative layer, TNC connector(s) and a thermal element. The outer conductor is positioned around the center conductor and the insulation layer is positioned between. The insulation layer has high thermal conductivity to provide substantial heat transfer between the center and outer conductors. TNC connector(s) are positioned at the end(s) of the connector and electrically coupled to the center and outer conductors. The thermal element is coupled to the outer conductor to conduct heat from the outer conductor to the heat sink. Heat sink connector providing transfer paths for bolted together RF components as well as individual RF power components.Type: GrantFiled: April 7, 2003Date of Patent: May 11, 2004Assignee: Com Dev Ltd.Inventors: Robert Leslie Lecsek, Shawn Robert Payne
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Patent number: 6731541Abstract: An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.Type: GrantFiled: May 14, 2003Date of Patent: May 4, 2004Assignee: Gennum CorporationInventors: David Kinsey, Luigi DiPede, James Kendall, Andrew Cervin-Lawry
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Patent number: 6728605Abstract: The present invention comprises a vehicle speed monitoring device which enables a driver to enter a speed tolerance profile that represents the driver's personal travel speed preferences and which alerts the driver when the vehicle speed falls outside the speed tolerance profile. Specifically, the speed tolerance profile consists of a number of speed tolerance ranges, each associated with a particular posted speed limit. As the vehicle travels through various map zones, the applicable posted speed limit is determined using a customized GPS map. The device determines the vehicle location, speed and the posted speed limit and then compares the vehicle speed using a running average to see whether vehicle speed is within the driver's speed tolerance profile and if not, the device provides the driver with a visual and/or audible warning according to the driver's operational preferences.Type: GrantFiled: May 16, 2002Date of Patent: April 27, 2004Assignee: Beacon Marine Security LimitedInventors: David M. C. Lash, Anthony B. Lash
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Patent number: 6631087Abstract: An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.Type: GrantFiled: May 9, 2001Date of Patent: October 7, 2003Assignee: Gennum CorporationInventors: Luigi Di Pede, David Kinsey, James Kendall, Andrew Cervin-Lawry