Abstract: A regulated plasma display power supply includes sequencing circuitry for triggering the high voltage power supply output only after other computer operational voltages are properly functioning. The power supply output is disabled if any of those operational voltages fail. A power supply short circuit protection scheme is included to prevent high power dissipation in the power transistor and possible damage to the regulator. Over-shoot protection is provided at the power supply input to protect the power supply components from over voltage spikes.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in either a FAST mode or a SLOW mode application programs written for a slow speed microprocessor. The slow speed microprocessor contains a pre-fetch queue that is smaller than the pre-fetch queue of the high speed microprocessor. A logic means is included, responsive to a mode select signal for controlling the wait state of said high speed microprocessor when in the SLOW speed mode so that every other word accessed to said RAM memory requires two consecutive word accesses to the same memory address to obtain the contents of the addressed location thereby enabling said high speed microprocessor to execute applications programs in the SLOW mode, on the average, at substantially the same speed as the program normally runs on the slow speed microprocessor.

Abstract: A mechanism for adjusting the height and viewing angle of a flat panel display which is viewed in conjunction with a portable personal computer. The mechanism includes a pair of arms that swing the display panel betwen the lowered and raised position, cooperating with a cam wheel moveable in a cam track. In a raised position, the flat panel display may be adjusted in viewing angle. In a lowered position the flat panel display may be securely latched to the portable personal computer to protect the display from damage.

Abstract: A personal computer is disclosed having a microprocessor RESET/HOLD arbitration circuit and logic. The RESET/HOLD arbitration circuit requires a RESET signal to wait until any pending microprocessor "HOLD" is serviced or in the alternative and in the event the "RESET" signal is being processed causes the microprocessor "HOLD" signal to wait. The priority arbitration circuit and logic is essential to the proper operation of the 80386 microprocessor particularly in shifting from the "protected" mode of the microprocessor to the "real" mode of the microprocessor, since many third party application programs require the use of the microprocessor "protected" mode and require that the microprocessor be "reset" before returning to the "real" mode. The microprocessor "reset" must be accomplished by resetting the microprocessor without resetting the entire machine and without losing a HOLD request during the RESET.

Abstract: An access window for use in fast food establishments and other similar drive-thru business establishments is disclosed. The window broadly comprises an elastic operating mechanism, two planar window members and a segmented articulated push-bar operator which is pushed to open the access windows. The push-bar operator can be locked in the open position. Upon releasing and/or unlocking the operator push-bar assembly the access window returns to its closed position by means of a closer bias member. The access window also comprises a locked window bias member which absorbs the pushing action on the operator push-bar, in the event the access window is latched shut, without damaging the access window and further without damaging the operating mechanism.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in either a FAST mode or a SLOW mode application programs written for a slow speed microprocessor. The slow speed microprocessor contains a pre-fetch queue that is smaller than the pre-fetch queue of the high speed microprocessor. A logic means is included, responsive to a mode select signal for controlling the wait state of said high speed microprocessor when in the SLOW speed mode so that every other word accessed to said RAM memory requires two consecutive word accesses to the same memory address to obtain the contents of the addressed location thereby enabling said high speed microprocessor to execute application programs in the SLOW mode, on the average, at substantially the same speed as the program normally runs on the slow speed microprocessor.