Abstract: An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative cache memory including a data store section for storing lines of data from the system memory and a cache directory for indicating, by means of line identifier fields at any time, the lines of the system memory data currently resident in cache, is provided with a way to improve the distribution of data across the congruence classes within the cache. A mechanism is provided for performing a permutation operation on an M bit portion (X) of the system memory address, which permutation determines the congruence class into which the address will map. The permutation mechanism performs a bit-matrix multiplication of said M-bit address with an M.times.M matrix (where M is a real positive integer greater than 1) to produce a permuted M-bit address (X').

Abstract: A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor.

Abstract: A known hand drawn stroke is serially sampled at different scales by n angle filters to provide n filtered known strokes at n different scales. An unknown hand drawn stroke is sampled in a like manner to provide n filtered unknown strokes at n different scales. Filtered unknown strokes are compared with filtered known strokes. If there is a comparison within predetermined limits at any scale, the unknown hand drawn stroke is recognized as being the same as the known hand drawn stroke.

Abstract: Method and apparatus for filtering a sequence of digital values representative of endpoints of vectors which represent the stroke of a writing instrument on a writing tablet. The cross-product and dot-product of the vectors comprising the stroke are computed to produce a sample of points which are close together where the stroke curves sharply, and which are further apart where the stroke is substantially straight.

Abstract: A method and apparatus for synchronizing two independent rasters, such that a standard TV video and a high resolution computer generated graphics video may each be displayed on a high resolution graphics monitor. This is accomplished utilizing dual frame buffers. A TV frame buffer, comprises a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resolution graphics monitor. A high resolution frame buffer in a computer is utilized to store high resolution graphics which is read out synchronously with the high resolution graphics monitor. A switching mechanism selects which of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion.

Abstract: A method and apparatus for performing a bit map search of the allocation state of memory pages in a computing system. A competitive search is accomplished by a pair of dedicated microprocessors, each of which implements a differently optimized search procedure, to find a bit indicating an un-allocated page in the memory. The first processor to find such a bit interrupts the other processor. The first processor then calculates the free page location and informs the computing system of the location. The other processor is responsible for updating the bit map and summary buffers.

Abstract: A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.

Abstract: A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.

Abstract: Apparatus for determining if, during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data, field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.

Abstract: A data shifter/rotator which is comprised of two levels of s, where s is an integer >2, way switches. The outputs of the first level are connected to the corresponding inputs of the second level. There are first and second control words, with the first control word controlling the amount of the shift/rotation in the first level, and the second control word controlling the amount of the shift/rotation in the second level. The amount of the shift/rotation is determined by the position of the s way switches in each level, as selected by the respective control words.

Abstract: In a computer network a logical duplex session between control points of adjacent network nodes is comprised of two physical half duplex sessions. Each half duplex session includes the send session of one node and the receive session of the adjacent node. In the event of a session failure at either node, the session from the other node is also deactivated so the nodes may begin recovery in phase with each other. Unique messages are exchanged between the adjacent nodes to distinguish new from old messages, such that the nodes are resynchronized only when new messages are present on each session.

Abstract: In a display system of the type where one or more symbol tables 20 are stored in general purpose storage and include blocks of data forming symbol definitions for each of a set of symbols, and an all points addressable (APA) display buffer 30 is provided which includes on-screen APA storage 32 for data indicative of pels to be displayed on a screen and off-screen APA storage 34 for symbol definitions with buffer control logic 36 for associating symbol definitions in off-screen APA storage with locations in on-screen APA storage such that symbols are displayed at desired locations on the display screen, cache control logic 42 is provided for copying the definition of a symbol for display from the symbol table in general purpose storage to off-screen APA storage if the definition for the selected symbol is not already held in off-screen APA storage, whereby the off-screen APA storage is configured as a cache for holding definitions for selected symbols.

Abstract: Apparatus for serializing 2.sup.M parallel outputs of an all points addressable memory into successive data groups, with each data group corresponding to a respective value for a pixel in an image, wherein the bit-length of the pixel value is selectable. The apparatus includes a gate circuit having 2.sup.M parallel input junctions connected to the outputs of the memory and 2.sup.N output junctions. The gate circuit selectively converts each set of 2.sup.M parallel inputs at the input junctions in to 2.sup.M-n successive data groups, with each group having a bit-length of 2.sup.n bits. Each such group is transmitted to 2.sup.n of the 2.sup.N output junctions. A communication element conveys to the gate circuit a signal which controls the bit-length 2.sup.n of the data groups, wherein n is an integer 1.ltoreq.n.ltoreq.N.ltoreq.M.

Abstract: Method and apparatus which restricts software, distributed on magnetic media, to use on a single computing machine. The original medium is functionally uncopyable, until it is modified by the execution of a program stored in a tamper proof co-processor which forms a part of the computing machine. The modified software on the original medium may then be copied, but the copy is operable only on the computing machine containing the co-processor that performed the modification.

Abstract: The lines representing each edge of each face of each object of a model for producing a multiple object image are segmented at line of sight intersections with other lines representing contour edges of visible faces. Each resulting edge line segment is checked against all visible faces to determine which are visible and which are invisible, and information on visibility is stored together with detailed information on each edge line segment for each object. The model is modified by changing the number of component objects and after each change checking the edge line segments for visibility only with respect to the changes associated with the changed component objects. This results in a substantial reduction in the required number of comparisons between segments and faces as compared to prior methods.

Abstract: An image processing system and a method for manipulating images in an image processing system where each image in the system is subdivided into a plurality of sub-images which are processed independently of one another. Control of each image and sub-image is maintained by means of a view state word or table so that only those portions of an image which are being actively processed require modification of their view state. The images stored in the system are maintained in a secondary store and only portions of the image are available for manipulation at any one time in a primary store. Manipulation of sub-images is determined by a modified Least Recently Used algorithm which minimizes data swaps between the primary and secondary stores.

Abstract: A multiple window display system includes a display device and a screen ownership area pointing to the identity of the window which is to contribute the data for each display area of the display device. An ordered list is maintained of the active windows in the priority order thereof. Means are provided to regenerate the screen ownership area from the ordered list, on each change made to the list, in terms of list position per device display area, by overwriting, progressing through the list in order of increasingly significantly priority order, the list indicating, in each position thereof, the identity of the window having the respective priority. The list contains the addresses of the windows in storage and the type thereof. The screen ownership area is reset to the lowest potential priority list position value and is overwritten.

Abstract: A system for establishing connections between processors in a distributed system of processors connected by a multiple multi-drop network. No wires are needed in addition to those already present in an existing network. In such a network connecting n processors, each processor is connected to all others by n identical multi-drop links. Links are assigned to processors on a one-to-one basis and a processor may transmit messages only on its assigned link. Processors may receive messages on any of these links, thereby enabling a processor to communicate with all others. The advantage of such a network over a single multi-drop link is that there is no contention for a shared link since each processor has a unique transmit line. In addition, no central control means is required for the network, as completely distributed control is utilized.

Abstract: A character compaction and generation method and apparatus which is particularly adapted to the compaction and generation of complex characters such as Kanji characters. Each character in a complex character set is defined by an I row and J column dot matrix, wherein each row is comprised of J bytes. Each successive row of a given character is scanned from the first through the Jth byte to determine if the current byte being scanned has the same numerical value as the immediately preceding or directly above byte in the scanning sequence. The number of successively read out sequence of bytes that have the same numerical value as the immediately preceding or directly above byte are coded as single symbols words Pn and Am, respectively, where n and m are integers which are indicative of the number of successive bytes scanned in sequence which are equal in numerical value to each immediately preceding or directly above byte.