Abstract: Provided are expression vectors for generating an immune response to a mucin. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal, a mucin antigen and CD40 ligand. Also provided are methods of generating an immune response against cells expressing a mucin by administering an effective amount of the vector. Further provided are methods of generating an immune response against cancer cells expressing a mucin in an individual by administering an effective amount of the vector. Still further provided are methods of overcoming anergy to a mucin self antigen by administering an effective amount of the vector.

Abstract: Provided are adenoviral vectors for generating an immune response to antigen. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal sequence upstream of a tumor antigen upstream of CD40 ligand, which is missing all or substantially all of the transmembrane domain rendering CD40L secretable. Also provided are methods of generating an immune response against cells expressing a tumor antigen by administering an effective amount of the invention vector. Further provided are methods of generating an immune response against cancer expressing a tumor antigen in an individual by administering an effective amount of the invention vector. Still further provided are methods of generating immunity to infection by human papilloma virus (HPV) by administering an effective amount of the invention vector which encodes the E6 or E7 protein of HPV. The immunity generated is long term.

Abstract: Provided are adenoviral vectors for generating an immune response to antigen. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal sequence upstream of a tumor antigen upstream of CD40 ligand, which is missing all or substantially all of the transmembrane domain rendering CD40L secretable. Also provided are methods of generating an immune response against cells expressing a tumor antigen by administering an effective amount of the invention vector. Further provided are methods of generating an immune response against cancer expressing a tumor antigen in an individual by administering an effective amount of the invention vector. Still further provided are methods of generating immunity to infection by human papilloma virus (HPV) by administering an effective amount of the invention vector which enocodes the E6 or E7 protein of HPV. The immunity generated is long term.

Abstract: A disk array subsystem for use in a data processing system. In one embodiment, the disk array subsystem comprises a generally rectangular chassis having a top wall, a bottom wall, a pair of side walls, an open front end and an open rear end. Disposed within the chassis are three power supplies, a pair of controller boards, a backplane, and a set of twenty disk drive modules. A mounting structure comprising four first disk drive module guide plates and a pair of second disk drive module guides is fixedly mounted within the chassis for removably mounting the disk drive modules in the chassis through the open front end and for placing the disk drive modules in approximate alignment with the backplane for electrical connection therewith. Each first guide plate is shaped to include five parallel slotted channels, and each second disk drive module guide plate is shaped to include ten parallel grooves.

Abstract: A data processing system is disclosed in which a plurality of high performance, intelligent, mass storage input-output devices are linked to a host controller by an input-output interface bus which is divided into three sections. Each section is completely independent of the other two sections and used for a different and specific purpose. One section is used to transfer commands and retrieve status information. A second section is used to handle device requests for data transfer and device signals for operation complete. The third section is used to transfer data to and from a device. Since the three sections are completely independent, simultaneous transfer of command control and data to different input-output devices or to a single input-output device can be performed.

Abstract: Methods and apparatus are set forth for quickly making switched virtual connections (SVCs) in a digital circuit switch that integrates voice and data using common switch, control and distribution equipment. SVCs provide concurrent data connection service from one station device, such as a PC, to other station devices over a single line for each station device where the line may also carry voice and terminal data service. A switch control processor remembers connection requests from station devices and acts on opportunities to utilize available bandwidth in an optimal manner. Dynamic connection reconfiguration techniques allow the system to "scavenge" bandwidth unused by voice or terminal data traffic for SVCs thereby providing the largest possible data rate at any given time. Short signalling messages and indexed values are used in order to speed activation time for previously defined connections while resource allocation is performed by the switch control processor to further enhance system operating speed.

Abstract: Methods are set forth which provide for the allocation of bandwidth for point-to-point, serial, bidirectional communication paths in a digital switching system. Bandwidth allocation is performed at both ends of a path (e.g. T1 line, IML, etc.) and may take place in either direction. Furthermore, according to the preferred embodiment of the invention, the Bandwidth Allocation Facility (BAF) at each end of a given path allocates bandwidth in integer multiples of maximum switching system granularity. The BAF also supports the implementation of user requests for any one of a plurality of allocation and boundary rules. To minimize the probability of contention and out of band signalling between the BAF pair associated with a given path, a front-to-back search mechanism is assigned for one BAF of the pair, while the other BAF utilizes a back-to-front search mechanism.

Abstract: An integrated office controller (IOC) network includes, in combination, a plurality of station devices each capable of transmitting and receiving multiplexed bearer and signal channel information; user port interface means for carrying said multiplexed information between a station device and a station multiplex/demultiplex device (SMX); a plurality of SMXs, each associated with and coupled to a predefined cluster of said station devices, via said user port interface means, for concentrating the multiplexed information froms said interface means into channel signals, central equipment module (CEM) means, including a call processor, a non-blocking switch matrix and clock means, for switching channel signals through said switch matrix under the control of said cell processor and clock means; transmission system means, capable of interfacing SMXs and trunk cards to said CEM, where said transmission system means includes modular line interface module (LIM) means for interfacing a plurality of SMXs and the CEM, an

Abstract: A data processing system having a local memory bus, a main memory coupled to the local memory bus and a host central processing unit coupled to the local memory bus includes a single input/output controller for interfacing a plurality of input/output devices to the local memory bus. The input/output controller includes a plurality of input/output device controllers, each input/output device controller being adapted to be connected to at least one input/output device, a single microprocessor for managing the overall operations of the input/output controller, a single buffer memory for storing a program of instructions for the microprocessor and temporarily storing data received from the input/output devices and a gate array for interfacing all of the input/output device controllers to the local memory bus.

Abstract: A data processing system in which the interface for connecting a host controller to a burst multiplexor channel comprises two sections one to handle the transfer of data and the other to handle the transfer of command and status information. The interface also includes logic to monitor the division of any transfer into bursts and logic to arbitrate for the two sections for any given burst.

Abstract: A data processing system which includes a central processing unit (CPU) to which is connected an I/O bus and a memory bus is disclosed. The data processing system further includes an I/O controller and a video control section. The I/O controller includes a terminal control section which is connected to the CPU through an RS232 Cable, an I/O control section which is connected to the I/O bus over a single line and a single processor for managing both the terminal control section and the I/O control section. The I/O control section includes a plurality of interface and control subsystems each for use with a separate peripheral device and an I/O bus interface and control subsystem. The terminal control section includes a video control section interface through which data is sent directly to the video control section over a separate line, and a keyboard interface for interfacing the terminal control section to a keyboard.

Abstract: A portable computer is sized to fit into a businessman's attache case and may be seated on a surface for use in either a normal position or a tilted forward position. The portable computer includes a housing having a base, a front top cover, a rear top cover and a foot door. The front top cover is pivotally attached to the front of the rear top cover and the rear top cover is fixedly attached to the base. Computer electronics (i.e. printed circuit boards), and two floppy disk drives are mounted inside the housing on the base at the rear and a full size keyboard is mounted inside the housing on the base at the front. A battery pack is disposed in the rear top cover of the housing. A full size liquid crystal display monitor is mounted on the front top cover. The foot door is movably mounted on the back of the base. When the front top cover is pivoted open the display screen is viewable and the keyboard is accessible.

Abstract: An input/output (I/O) device controller for a data processing which is implemented on a single printed circuit board, includes a terminal control section, an I/O control section, a processor section and a timing generator section. The terminal control section includes a keyboard interface, an RS232 interface for transmitting and receiving data from the system host CPU over an RS232 line, and a video control section interface. The I/O control section includes a plurality of different I/O interface and control units for connecting the section to a number of different I/O devices and a system I/O bus interface and control unit for interfacing the section to the system I/O bus. The processor section manages the operations of the terminal control section as well as the I/O control section.

Abstract: A video control section for a data processing system for controlling a CRT display is disclosed. The video control section includes a video memory comprising an array of dual port RAMS which is connected through an interface to the system memory bus, a shifter, a palette, a D/A converter, an oscillator section, a timing and synchronizer section and a microprocessor. The microprocessor, which is connected to the system memory bus through an interface, manages the overall operations of the video control section to generate video signals for the CRT display and in addition along with the oscillator section and timing and synchronizer section generates all of the video timing and control signals for the CRT display.

Abstract: A control and switching device which is installed at a customer's computer (local) site and which links a remote terminal by modems over telephone lines to the system console, the TTO/TTI port and the ALM/IAC port of the host computer, and to a user terminal for remote diagnosis of hardware and software problems is disclosed. The device, which is coupled by separate lines to the modem at the local site, the system console, the user terminal the TTO/TTI port and the ALM/IAC port of the host computer includes a microprocessor a memory, various logic and control circuits and a three position keyswitch. The keyswitch provides a first level of security and limits the type of access allowed by a remote caller. When the switch is in a first position, the caller has no access to the host system. When the switch is in a second position, the remote caller can connect to the ALM/IAC port or communicate with the user terminal but cannot change configuration data.

Abstract: A control and switching device which links a remote terminal by modems over telephone lines to a local central processing unit (CPU) and a local computer console terminal is disclosed. The device, which is coupled by separate lines to the modem at the local site, the local console and the TTY and ASYNC ports of the CPU, includes a microprocessor, a memory, logic circuits and a switch assembly. The switch assembly includes first, second and third switches which are interlocked and which allow three different levels of remote access of the remote terminal. When the first switch is depressed, the device is powered down, the remote terminal has no access to either the TTY or ASYNC ports of the CPU and the local console is hardwired through the device to the TTY port of the CPU. When the second switch is depressed, the local console is hardwired to the TTY port of the CPU and the remote terminal is electrically connected to the ASYNC port of the CPU.

Abstract: Apparatus and methods for the calculation of addresses of data items in digital computer systems which perform call and return operations. In the digital computer systems of the invention, items of data called immediate names represent other items of data and specify how the address of the represented item is to be calculated. Certain immediate names represent items of data whose addresses are calculated using linkage pointers. Such an immediate name specifies the linkage pointer to be used in the calculation. Linkage pointers are pointers whose values remain unchanged during an execution of a procedure. When the digital computer system's processor executes the call operation, the processor places the addresses represented by the linkage pointers in internal registers.

Abstract: A method for executing call and return instructions in a digital computer system operating under control of microcode. The microcode may specify calls to and returns from sequences of microinstructions. A call microinstruction sequence corresponds to the call instruction. The call microcode in turn calls other microinstruction sequences for deriving pointers representing the location of the called procedure and of arguments from operands in the call instruction. As the call microcode obtains each argument pointer, it places the pointer on the stack. After it has obtained all of the argument pointers, it passes the pointer to the called procedure and a pointer to the argument pointers to a general call microinstruction sequence. That microinstruction sequence locates the called procedure, makes a new frame including the argument pointers, and saves the state necessary to resume execution of the call microinstruction sequence itself.

Abstract: An intelligent asynchronous controller (IAC) for use in operably coupling a plurality of asynchronous input/output (I/O) devices to a host central processing unit (CPU) is disclosed. The IAC is designed and programmed to control the transfer of data between the plurality of I/O devices and the CPU, to perform character processing on the data received from the I/O devices before transmission to the host CPU and to perform other types of data processing.

Abstract: A system for performing operations on data items in digital computer systems in which the instructions may not specify internal registers in the processor as destinations of data received from memory or sources of data provided to memory. The system includes a result memory, apparatus for executing operations, instructions containing operation codes which specify that the result memory is to be a source of data to be operated on by the apparatus for executing operations, and control apparatus responsive to the operation codes for controlling the apparatus for executing operations. The result memory stores only the results of previous operations and may serve only as an input to the apparatus for executing instructions. The apparatus for executing operations may receive items to be operated on from either the computer system memory or the result memory.