Patents Represented by Attorney Jacqueline Garner
  • Patent number: 6122041
    Abstract: A liquid cooled light pipe is disclosed which allows effective pyrometric temperature measurements using a remote detector. Temperature of the light pipe assembly is controlled and maintained at an approximately constant value in order to establish good long-term temperature measurement accuracy. The temperature-controlled light pipe assembly of this invention can be used for multi-point temperature measurements of a heated body with good spatial resolution for real-time multi-zone temperature control applications.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: September 19, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Habib Najm, Mehrdad M. Moslehi
  • Patent number: 5535241
    Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: July 9, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Shivaling S. Mahant-Shetti, Robert J. Landers
  • Patent number: 5525814
    Abstract: A three dimensional latch and bulk silicon pass transistor for high density field reconfigurable architectures is provided utilizing bulk silicon with a layer of polysilicon or silicon on insulator (SOI) thereover. The pass transistor, which must have very low resistance to provide a good short circuit path between the metal runs and fast switching speed, is fabricated in the bulk silicon wherein the resistivity can be made very low relative to polysilicon and because only the pass transistor is disposed in the bulk silicon, thereby permitting the dimensions thereof to be increased to provide even lower resistance. Since only the latch is fabricated in the layer of polysilicon or SOI and is disposed over the pass transistor, the amount of chip area utilized can be the same or less than required in the prior art wherein all circuitry was in the bulk silicon.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: June 11, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Satwinder Malhi