Abstract: In a computing system having a plurality of storage devices, notification of an application program of a change of state in a storage device so that corrective action can be taken. A notification module creates and maintains an event queue for storing events corresponding to changes in the state of the storage devices. The notification module indicates to the application programs that events are in the queue. The queue conditions are monitored by the notification for queue maintenance.

Abstract: A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Abstract: In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

Abstract: The present invention provides a user control mechanism for selectively retaining for display a document obtained from a network. The user control is located as an icon or symbol in the browser interface for ease of use. Subsequent documents which are downloaded from the network are displayed in a separate window of the display in the computing system, and these subsequent windows are also provided with the same user control mechanism. In particular, the user can selectively create a second browser display page by following a link contained in the first browser display page, without overwriting the contents of the first browser display page.

Abstract: A file system for use in a network computer system has a server file system in the server, which contains at least some file elements to be selectively accessed by the client. An overlay file system is assigned to the client within the server, and contains at least some file elements that have corresponding file elements in the server file system. The overlay file system is configured to provide an overlay file system element to the client when the file element exists in the overlay file system, and to allow access to a server file element when a corresponding file elements does not exist in the overlay file system. Through the use of such file system, a network file system can be configured to allow the client to write to it, with the appearance to the client that it is writing directly to the server file system.

Abstract: In a multiprocessor system, a method, apparatus, and article of manufacture for maintaining the proper sequence of store/write operations between multiple processors to remote I/O devices without requiring changes to application software. A synchronizer is employed to synchronize write operations to the remote I/O device, and the write operations are synchronized individually upon detection and emulation, or as a group upon detection of the release of a mutual exclusion lock.

Abstract: In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an instruction identifier and the destination register specified by the live instruction. The table can also contain information about the age of the entry, the validity of the entry, and the process which the entry is associated. A dependency between instructions is determined by one or more comparators comparing the destination register to the source registers of the current instruction. True dependencies are distinguished from false dependencies using the age information, the validity information, and the process information.

Abstract: Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart memory entry to trace inconsistencies between the cache entry and the memory entry and to correct the cache entry. A page table entry in memory with a zero mapping mark is checked against a counterpart page entry in a translation lookaside buffer. Inconsistencies between the page table entry with a zero mapping mark and the existence of a counterpart page entry in the translation lookaside buffer is traced. The inconsistency is corrected by deleting the counterpart page entry in the translation lookaside buffer. Address mapping is checked comparing a page entry in the translation lookaside buffer against a counterpart page table entry in the memory. Inconsistencies between the page entry and the page table entry are traced and corrected.

Abstract: In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having four possible register dependencies is converted into two microinstructions which are processed normally within the processor. The first microinstruction is coded to perform the arithmetic operation specified by the single-precision instruction using the first and second source registers specified and storing the result in a phantom register. The second microinstruction is coded for merging the contents of the phantom register and the destination register specified. Each microinstruction has at most two possible register dependencies, thereby reducing the total number of register dependencies which the processor is required to track.

Abstract: In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper logic for expanding complex instructions into microinstructions. Control logic parses a bundle of instructions into sub-bundles of non-complex instructions and sub-bundles of microinstructions. The control logic detects when a complex instruction is present in a bundle of instructions and directs the complex instruction to the helper logic for expansion into two or more microinstructions. Each non-complex instruction bypasses the helper logic, thereby improving the execution performance of the non-complex instruction.

Abstract: In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

Abstract: A method and apparatus for storing associated data in a computing system having two or more storage devices arranged in a RAID configuration. The storage devices have a prewrite area for pre-storage of the data, and data region for persistent storage of the data. A scoreboard memory structure is created for monitoring the state of the prewrite area, and data in the prewrite area is conditionally invalidated based upon the information contained in the scoreboard memory structure. By conditionally invalidating the prewrite data, the write performance of the RAID storage system is improved.

Abstract: In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an instruction identifier and the destination register specified by the live instruction. The table can also contain information about the age of the entry, the validity of the entry, and the process which the entry is associated. A dependency between instructions is determined by one or more comparators comparing the destination register to the source registers of the current instruction. True dependencies are distinguished from false dependencies using the age information, the validity information, and the process information.

Abstract: A pole-trimmed writer for an MR read/write data transducer which may be produced without significant re-deposition of Al.sub.2 O.sub.3 or NiFe on the sides of the writer poles. The process disclosed herein advantageously provides an upper (top) pole which is processed to project a pair of relatively thin, laterally extending lower flanges, prior to the use of the upper pole as a mask to subsequent ion milling of the lower pole, or shared shield. In a preferred embodiment, the process for producing the flange is implemented in conjunction with the deposition of a single copper (Cu) or dual Al.sub.2 O.sub.3 and chromium (Cr) overlayers formed on the upper pole seed layer followed by the top pole formation and selective removal of a predetermined amount of the underlying portions of the gap material prior to a subsequent ion milling operation and further processing of the read/write head.

Abstract: A pre-biasing technique for a transistor-based avalanche circuit which improves the initial rate of rise in the current applied through a laser diode or other light emitting device in a laser based distance measurement and ranging instrument and, therefore, the sharpness of the leading edge of the laser pulse produced. Since the timing of the flight time of a laser pulse to a target and back to the ranging instrument is determined with reference to the leading edge of the emitted laser pulse, the inherent precision obtainable is enhanced by the production of a sharper leading edge pulse. Through the use of the pre-biasing technique disclosed, the very rapid rise time pulse which may be achieved also allows for the substitution of a much cheaper light emitting diode in lieu of a conventional laser diode in an alternative implementation of a light pulsed-based distance measuring and ranging instrument.