Abstract: A piezoelectric actuator control circuit includes a first conductor attached to the free end of a piezoelectric device and a second conductor rigidly fixed at a position spaced from the piezoelectric device such that a variable capacitor is created between the first and second conductors. The variable capacitor is then used in a capacitive voltage divider to generate a drive signal which moves the piezoelectric device. Thus, the movement of the piezoelectric device can be precisely controlled. The control circuit allows for precise control of an array of such piezoelectric actuators and is particularly applicable to the use of actuators for controlling a mmWave phase array antenna.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Abstract: An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU.sub.-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: A notebook computer (100) or other electronic device has a keyboard (106) using keys (40, 80) which can assume an active state for typing while a spring (64, 84) is pressed against a guide mechanism (44). By disengaging the spring (64, 84) from the guide mechanism, the keys (40, 80) assume a storage state at a lower height.

Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A shallow etch stop trench (46) is first ion milled around each ceramic island on front side and then filled with an etch stop material (e.g. parylene 48). An optical coat (e.g transparent metal layer 54, transparent organic layer 56 and conductive metallic layer 58) is elevated above the etch stop material by an elevation layer (e.g. polyimide 49). For some applications, it has been experimentally verified that there is no loss, and sometimes a measured increase, in optical efficiency when the optical coating is not planar in topology. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 86) containing a massive array of sensing circuits.

Abstract: A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ("MPU" 102), a peripheral processing unit ("PPU" 110) that communicates with the MPU and a peripheral control unit ("PCU" 112) capable of communicating with the PPU and with at least one associated peripheral device. The PCU has associated therewith a first number, m, of interrupts for signalling to the MPU. The MPU has a second number, n, of interrupt channels over which interrupts are communicable to said MPU. A first register (IN1616) is provided in the PCU for storing a routing value representing the assignment of the m interrupts of the PCU to a selected subset of m channels of the n interrupt channels. A second register (IN1222) is provided in the PPU for storing the routing value. A number, m, connections are provided between the PCU and the PPU for transmitting the m interrupts from the PCU to the PPU.

Abstract: A digital color transient improvement (CTI) method and apparatus for enhancing the color sharpness of a chrominance signal by increasing the steepness of color edges without ringing. A median logic circuit (30) samples three signals A, B and C, and selects values from these three signals to provide an output signal that has steep color edges. One signal (A) is the non-processed input signal, a second signal (C) is a twice delayed input signal, and the third signal (B) is the derivative of the once delayed input signal. The present invention is ideally utilized by an SVP and requires a minimum number of instructions, but can also be implemented by a small number of gates on an ASIC or FPGA.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.

Abstract: This invention is useful in column multiplexed memories, particularly static random access memories (SRAM) used in application specific integrated circuits (ASIC) . These column multiplexed memories include memory cells disposed in rows and columns. For writes all the bitlines are connected to a bias generator. The bias generator uses first P-channel field effect transistor and a first N-channel field effect transistor connected in series with their junction connected to the bitline. The bias generator is driven by a bias enable pulse that is active for a short time before the write time. Normally these field effect transistors are biased OFF by a second P-channel field effect transistor and a second N-channel field effect transistor. Another pair of N-channel field effect transistors connect the bases of the first P-channel field effect transistor and the first N-channel field effect transistor together to the bitline when the bias enable pulse is active.

Abstract: The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a portable computer. A portable telephone (166) is constructed to fit within a cavity (210) in a portable computer (164). When fully inserted into the computer (166), the portable telephone (166) is physically connected to the portable computer (164) by a latching mechanism and communicates with the portable computer by means of a computer/portable telephone interface (172, 192, 204 that electrically connects the portable telephone to the portable computer. Physically and electrically connecting the portable telephone to the portable computer eliminates the need for a cable or tethered connection between a portable computer and a portable telephone. In one embodiment of the invention, the portable telephone serves as the portable computer's modem and function while installed in the computer.

Abstract: In one embodiment there is a comparison circuit (28) for selecting data in response to a first binary quantity (ADDRESS) and a second binary quantity (TAG). The comparison circuit includes a match circuit (34) for outputting a match signal (MATCH) in response to comparing the first binary quantity and the second binary quantity. The comparison circuit also includes a delay circuit (36) for outputting a delay signal (TC.sub.D) in response to a signal generated at a same time as the second binary quantity, and circuitry (38) for outputting a hit signal in response to the match signal and the delay signal. The hit signal indicates that a memory stores data corresponding to the second binary quantity. Still further, the comparison circuit includes dynamic select circuit (40) for outputting a logic state of data corresponding to the first binary quantity and in response to the hit signal.

Abstract: A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits.

Abstract: In one embodiment, a kit for reusably attaching an identification transponder 22 to an object 16 to be identified is disclosed. The kit includes an outer sleeve 10, an inner package 12 and, optionally, a release tool 14. The outer sleeve 10 is preferably formed of a non-electrically conducting material and includes an outer locking mechanism 18 disposed therein. The inner package 12 will store the identification transponder 22 and includes an inner locking mechanism 20 for cooperating for with the locking mechanism 18 within the outer sleeve 10. The inner package 12 is operable to be secured within the outer sleeve 10 when the inner locking mechanism 20 and the outer locking mechanism 18 are engaged. If included, the release tool 14 can be used for removing the inner package 12 from the outer sleeve 10 by disengaging the inner locking mechanism 20 from the outer locking mechanism 18.

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934, 51, 97), first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934, 51, 97), a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an interface between the notebook computer and the docking station to transfer DMA related information between the DMA controller and a requesting device in the docking station.

Abstract: A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources.

Abstract: This is a system and method of intelligently terminating power to a computing device. The system may comprise: a processing device; a power source connected to the processing device; a switch connected to the power source; and a control system run by the processing device and connected to the power source and the switch. In addition, the system may include a deadman timer which provides a fail-safe operation. Further, the system may include a method and apparatus for executing an orderly shut down procedure for software and hardware. Moreover, the system could be tied to a thermal and/or power management system. Additionally, the system could initiate an orderly shut down of peripheral devices connected to the system serially or by parallel connections. Other devices, systems and methods are also described.

Abstract: A method for encoding information bits to derive a cyclically encoded group of code bits from the information bits that were encoded, using a computer processor. A sequence of data states are generated that are the result of a series of exclusive OR operations of each of the code bits with each of the bits of a first generator word and bitwise ANDing each of the resultant bits with the results of the next previous such exclusive OR operations shifted in the direction of the least significant bit ("LSB") so as to generate a data state. The invention involves the following steps. First, an initial data state of zero is provided. Next, the LSB of the code bits is bitwise exclusive ORed with the current data state. Next, the result of the previous step is bitwise ANDed with the value n, where n is a selected binary value 2.sup.x -1, where x is any positive integer. Next, the current data state is changed to the next sequential data state by changing the data state to one of 2.sup.