Abstract: The electromigration characteristics of integrated circuit conductors are determined by passing a high current for a short period of time through an inventive test structure. This provides a rapid test in a more accurate manner than with the prior art SWEAT (Standard Wafer-level Electromigration Accelerated Test) structure. The test results have been found to be well correlated with long-term low current electromigration tests. A sensitive differential test may be implemented that determines the effects of topography features. The inventive test technique can be performed on every wafer lot, or even every wafer, so that adjustments to the wafer fabrication process can be rapidly implemented.

Abstract: A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V.sub.SS), and the underlying semiconductor region is connected to the positive power supply conductor (V.sub.DD). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.

Abstract: A resist is formed by sorption of an inorganic-containing gas into an organic material. The development of the resist occurs by exposure to a plasma (e.g., oxygen reactive ion etching) that forms a protective compound (e.g., a metal oxide) selectively in the resist. The selected regions can be defined by patterning radiation of various types, including visible, ultraviolet, electron beam, and ion beam. In an alternate embodiment, the selected regions are defined by an overlying resist, with the gas sorption protecting the underlying layer in a bilevel resist. The protective compound can protect the organic resist layer during etching of an underlying inorganic layer, such as metal, silicide, oxide, nitride, etc.

Abstract: An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

Abstract: When performing fixed point multiplication with 32 bit operands for example, the product is, in general, represented by a 64 bit number. However, a typical microprocessor may compute the product to only 32 bits. Therefore, the possibility of overflow exists. The present invention provides an indication as to the status of the upper (most significant) 32 bits of the product. This indication may include both "carry" and "overflow" flags, which are unsigned and signed overflow, respectively. The inventive technique is implemented in hardware that is used in conjunction with a Booth recoding multiplier.

Abstract: An integrated circuit having an analog-to-digital converter includes built-in self-test (BIST) circuitry. The BIST circuitry checks for monotonicity, and typically also that all possible codes are present, by applying a ramp voltage to the A/D input, while a state machine monitors the output. The state machine can check to ensure that the output increases by only one least significant bit (LSB) each time the output changes. A counter may be checked at the end of the test, to ensure that all the possible codes are obtained. The BIST circuitry may be activated, and the results monitored, through package terminals after the chip is packaged, thereby allowing for boundary scan testing. The inventive technique may be used to save testing costs during manufacture. In addition, system diagnostics in the field can become more cost effective.

Abstract: An output buffer provides for additional current sinking or sourcing capability by switching in an additional transistor when the output voltage passes a given level. This allows the output buffer to supply DC current to a load without requiring an excessively large AC drive capability, which could undesirably increase switching noise. In a typical embodiment, an inverter senses when the buffer output voltage reaches its switching threshold (approximately V.sub.DD /2), and turns on the additional transistor after a given delay. For example, a CMOS output buffer driving a TTL load may obtain additional current sinking capability by this technique. On-chip buffers (e.g., bus drivers and clock drivers) can also benefit from this technique.

Abstract: A latch circuit employs a feedback arrangement comprising a transmisson gate circuit that conducts only when the output node is in a mid-voltage state. At the onset of a metastable state, the feedback arrangement forces a receiving node into its previous stable state, thereby forcing the output node into a stable state. This eliminates or reduces the possibility that the latch could remain hung for an indefinite period in a metastable state.

Abstract: A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide having a p-type channel stop region formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxide region that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n-channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries.

Abstract: In certain circuits, it is desirable to match the electrical characteristics, (e.g., thresholds), of two (or more) MOS transistors. For example, in an ECL output buffer, a first transistor is a voltage reference, and a second transistor is an output buffer controlled by this voltage reference. However, the orientation of the transistors may affect their electrical characteristics. This may be due to the source/drain ion implantation step that occurs at an angle off the vertical, or other processing effects. The present invention provides symmetrical MOS transistors having characteristics that are independent of orientation. For example, a square gate layout provides both vertical and horizontal current components, thereby obtaining 90 degree rotational symmetry.

Abstract: An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.

Abstract: An integrated circuit includes a conductive fusible link (14) that may be blown by laser energy. The dielectric material (15) covering the fuse is etched away to expose the fuse. A protective dielectric layer (30) is formed on the fuse to a controlled thickness less than that of the interlevel dielectric. The resulting structure prevents shorts between conductors that might otherwise occur due to debris from the fuse-blowing operation, and provides protection to the integrated circuit. In addition, the fuse blowing operation is more consistent from fuse to fuse.

Abstract: An output buffer maintains low noise across a range of process variations, temperatures, and voltages. This is achieved by limiting the drive signal so as to reduce the switching speed of the output buffer as the other variables tend to increase the speed. This is accomplished by limiting the current through the pre-driver stage by controlling the conductance of a shunt transistor connected to a grounded capacitor.

Abstract: A lightwave receiver, suitable for CATV applications, includes an input photodiode that is capacitively coupled to the differential inputs of a balanced amplifier. Biasing of the photodiode may be achieved by connecting the photodiode in series between a pair of resistors, with the differential inputs being taken from either side of the photodiode. This arrangement avoids the use of a transformer, which exhibits considerable high frequency loss, thereby avoiding the bandwidth limitation inherent with a transformer.

Abstract: In a method of fabricating semiconductor integrated circuits, the effects of mobile ion contamination in a dielectric layer which has been subjected to a source of mobile ion contamination, e.g., reactive ion etching, is substantially eliminated by removing substantially only the topmost portion of the dielectric layer, e.g., 10-15 nm of an 800 nm layer, promptly after performing the step which produced the source of contamination.

Abstract: An integrated circuit formed on a substrate has field effect transistors formed in relatively lightly doped (i.e., high resistivity) epitaxial layer, typically in a "tub" formed therein. Operating current for the transistors is provided at least in part through a metallic layer on the back side of the substrate. Surprisingly, the conductivity is sufficiently high through the epitaxial layer and the substrate that the number of power supply bondpads on the front side may be reduced, or eliminated entirely in some cases. In addition, a reduction in power supply lead inductance is obtained, reducing ringing and ground bounce problems.

Abstract: When making CMOS logic circuits, for example an inverter, it is frequently necessary to connect the sources of the p and n channel transistors to their respective tubs (n and p, respectively). The prior art required either a large contact window covering both source and tub regions, or else two standard size contact windows. The present technique forms the tub tie connection by the use of the same silicide layer that is formed on the source/drain regions, which typically also forms a gate silicide in the self-aligned silicide (i.e., "salicide") process. A conventional window may then be used to connect the silicide tub tie (and hence the source/tub regions) to a power supply conductor. A space saving is obtained, and increased freedom for placing the power supply contact window is obtained.

Abstract: An improvement in silicon wafer flatness is obtained by reducing the time spent in polishing the wafer. After a conventional lapping operation, the wafer is coated with an etch resistant coating, typically silicon nitride. A polishing step removes the nitride coating on the flat surfaces of the wafer, but leaves a nitride coating on the sides of pits that are formed in the lapping operation. The wafer is then etched, typically in KOH, to remove the silicon surface to below the depth of the pits. The undercutting of the nitride coating removes the pits, or leaves relatively small protrusions in their place. The protrusions may be removed by a short polishing operation. Other wafer types and etch-resistant materials are possible. Integrated circuits are typically formed on the wafers by lithography techniques that advantageously utilize the improved flatness.

Abstract: A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.

Abstract: Deposited silicon dioxide may be used as a field oxide layer or for other dielectric purposes in integrated circuits. However, etching a pattern in the layer usually produces steep sidewalls that prevent good step coverage of subsequently deposited conductor layers. The present technique forms the dielectric in at least two layers having different densities. A sequence of anisotropic and isotropic etching results in stepped sidewalls, providing good linewidth control and good step coverage of subsequently deposited material.