Abstract: A relatively high speed memory system is provided utilizing relatively low speed electronic memory devices such as NOS integrated circuits. The memory system is organized as a planar array with rows and columns of word positions and includes an address generator for generating sequences of N address bits to access sequences of N words of data where N is greater than 1 along any selected substantially straight path in any direction along the memory array with each address generating having a set of most significant bits and a set of least significant bits. Each electronic memory device includes an address decoder which is responsive to a first plurality of address bits for selecting a memory element within the memory device and an enable circuit for enabling the memory device. The logic circuit coupling the address generator to the electronic memory devices selectively enables at least one memory device during each memory access and no one memory device is selected more than once per N memory access.