Abstract: A two phase charge coupled device memory array wherein the storage capacity is increased by using multiple levels of charge storage within a given cell. A voltage waveform generator capable of producing one of four different voltages is utilized to input and output charge in the multiple level charge method. In determining the level of charge stored within a given cell in the array, the voltage difference between a reference cell and an adjacent addressing cell is used. By determining the voltage level of the addressing cell at which charge overflows the reference cell and counting the number of times it overflows as the voltage generator is successively stepped through its four voltage levels, the level of the original charge input to a given cell can be determined. To make the multiple level scheme independent of process parameters and temperature, the same two cells are utilized for both input and output functions. Various other cells are provided to block and route charge with respect to the array.

Abstract: A method and apparatus for applying focus correction to an E-beam or charged particle system to compensate for wafer warp and mask tilt. In an electron beam system including a registration system which measures the position of four registration marks with the beam and calculates the apparent magnification error of a given chip, means are also provided for using magnification and rotation error information to calculate a height error factor and to apply a compensating current to a dynamic focusing coil of the electron beam to move the effective beam focal plane to a position which matches the wafer or mask plane at each chip site.

Abstract: In an ion beam apparatus a structure for controlling the surface potential of the target comprising an electron source adjacent to the beam for providing electrons to the beam and means between the target and source for inhibiting rectilinear radiations, i.e., electron and other particle and photon radiations between said source and said target. This prevents heating of the target by the electron source and cross-contamination between the source and the target.

Abstract: In an ion beam apparatus a structure for controlling the surface potential of the target comprising an electron source adjacent to the beam for providing electrons to the beam and means between the target and source for inhibiting rectilinear radiations, i.e., electron and other particle and photon radiations between said source and said target. This prevents heating of the target by the electron source and cross-contamination between the source and the target. The apparatus further includes means for maintaining said shield means at a lower temperature than said target.

Abstract: An improved composite channel field effect transistor and method of fabrication, which exhibits high density characteristics and yields high performance with less sensivity to threshold shift due to hot electrons when operated at high source to drain voltage levels.

Abstract: A real time monitoring and control system for single or multi-fired combustion systems which permits adjustment of the air fuel ratio in the system for optimized efficiency and minimized pollution content in the exhaust gas, while providing safety control of the combustion process. The system includes a high sensitivity light sensor which is utilized to monitor the combustion flame and provide an electrical output proportional to flame temperature, that is utilized to control the air fuel ratio of the system. The wavelength sensitivity of the sensor is capable of selection, for example by selection of sensor type and/or use of appropriate filters, to monitor a predetermined range or region of the flame emission spectrum in order to enable correlation of the intensity of the emission spectrum of the type of fuel being utilized, i.e., oil or natural gas, with temperature and combustion efficiency.

Abstract: A variable increment phase locked loop circuit designed for use in a digital data communications system wherein a data input signal is synchronized with a local feedback signal by means of comparing the data input signal and the local feedback signal, and providing frequency adjustments to the feedback signal that are proportional to the instantaneous deviation between the data input signal and the feedback signal. In one embodiment, the circuit is not responsive to deviations between the data input signal and the feedback signal that are less than a preset threshold value. The output of the circuit is useful as a stabilized system clock signal.

Abstract: A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.

Abstract: A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

Abstract: An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, ##EQU1## AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS C.sub.P =.sqroot.C.sub.(P.sub.-1) .sup.. C.sub.(P.sub.+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one.

Abstract: A non-volatile memory cell that includes a Schottky barrier diode, located over a sub-diffused line or region formed within the substrate, acting as the control element. Information is stored in the device by introducing electrons into a nitride-oxide interface located at the perimeter of the Schottky barrier junction. Thus, the injected electrons are subject to trapping in the nitride-oxide layer, causing depletion in the epi region adjoining the diode interface, thereby influencing the current carrying state of the device.

Abstract: A high density low profile air cooled wafer package including flip chip and embedded logic or memory islands upon a wafer package mounted within a heat dissipating cover having improved thermal dissipation. Heat dissipation is achieved through a thermal grease interface provided between the wafer carrier and the heatsink cover, with pressure being applied to the interface by partially deflected electrical connectors secured there between.

Abstract: In an ion implantation apparatus, means for forming multiple, separate parallel ion beams, each having a predetermined spot diameter, and means for focusing each of said ion beams upon a predetermined chip area of a target wafer whereby multiple chip areas upon the wafer can be simultaneously implanted with prescribed ion dosages.

Abstract: A novel method and apparatus for achieving electrostatic deflection of high current ion beams within a scanning apparatus. In one embodiment, a pair of gates are provided, with one gate being oriented proximate each side of the deflection plates, and each gate being biased to a negative voltage of a sufficient amplitude to repel electrons which otherwise would be attracted to the positively-biased deflection plates to thereby protect the electron cloud from degradation, and maintain space charge neutralization of the ion beam. In another embodiment, means are provided to drive the deflection plates at negative voltages at all times and to maintain portions of the ground tube of the apparatus adjacent the deflection plates at a ground or negative level in order to avoid degradation of the electron sheath.

Abstract: A method is disclosed for forming Schottky barrier junctions having improved barrier height characteristics. The method involves the use of a layer of polysilicon deposited upon the Schottky metal prior to sintering. The polysilicon layer acts as a source from which silicon is diffused into the metal during the sintering operation. After sintering the junction is quenched or cooled at a rapid rate whereby outdiffusion of the silicon is prevented.

Abstract: A shielded magnetic lens and deflection yoke structure for an electron beam column which minimizes aberrations in the lens system caused by winding asymmetry in the field coil, as well as aberrations due to eddy currents created within the magnetic circuit of the lens by interaction with the field of the deflection yoke. The shield includes a polepiece structure for the magnetic electron lens generally comprising a hollow cylinder formed of a plurality of precisely machined magnetic discs stacked concentrically with precisely machined nonmagnetic discs in alternating sequence with the lens coil positioned adjacent the periphery of the cylinder and the deflection yoke positioned within the cylinder or proximate to either end thereof. In one preferred embodiment of the invention the magnetic discs are formed of a nonconductive material such as ferrite and the nonmagnetic discs are formed of alumina.

Abstract: A dual channel high gain differential amplifier utilizing enhancement depletion MOS field effect transistors which exhibits high common mode rejection and fast switching characteristics.

Abstract: A multi-layered package for a magnetic domain device including self-contained in-plane switching magnetic field coils surrounding one or more magnetic domain device chips and a permanent magnet surrounding the switching magnetic field coils. The switching coils are formed by two printed circuit layers, each layer comprising an insulating substrate having striped conductive patterns orthogonally oriented relative to each other on the opposite surfaces of the insulating layer. The ends of the striped conductors on one printed circuit layer are connected to the ends of the corresponding striped pattern on the other printed circuit layer so as to form one of the switching coils. The ends of the other pair of striped conductive patterns are similarly connected to form the second switching coil. The magnetic domain device chips are placed inside the formed switching coils which, in turn, are surrounded by the permanent magnet.