Patents Represented by Attorney, Agent or Law Firm James M Trygg
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Patent number: 4779335Abstract: A tool for crimping electrical terminals (10) to terminate conductive wires (20) by inelastic deformation of portions of the terminal includes a motor driven cam (42) connected to toggle linkage (48) adapted to drive a double acting linkage (30,32) to effect die displacement against the terminal through a disk (78) mounted for rotary movement in a race (80), the double acting linkage providing an enhanced mechanical advantage in the high force requirement zone of die displacement.Type: GrantFiled: July 29, 1987Date of Patent: October 25, 1988Assignee: AMP IncorporatedInventors: Benjamin Schwartzman, Robert Volinskie
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Patent number: 4777680Abstract: A musical potty chair is disclosed having a novel mechanism for effecting operation of a music box upon elimination into a receptacle by a child using the device.Type: GrantFiled: June 28, 1983Date of Patent: October 18, 1988Inventor: Lirida Paz
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Patent number: 4755481Abstract: A silicon-on-insulator (SOI) device is fabricated by forming at least one island of semiconductor material on a surface of an insulating material. Silicon is then formed on the areas which surround the at least one island. The silicon is oxidized to form silicon dioxide regions which surround the at least one island.Type: GrantFiled: May 15, 1986Date of Patent: July 5, 1988Assignee: General Electric CompanyInventor: Lorenzo Faraone
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Patent number: 4751561Abstract: A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.Type: GrantFiled: April 2, 1987Date of Patent: June 14, 1988Assignee: RCA CorporationInventor: Lubomir L. Jastrzebski
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Patent number: 4741212Abstract: A method and apparatus for determining the location and size of structural defects in a body of solid material, particularly regions of thermoplastic deformation in semiconductor wafers. An acoustical focused beam generated by an ultrasonic transducer, having a pulsed frequency of at least 75 MHZ, is transmitted through the body to provide an attenuated signal pattern which manifests structural defects, such as slip planes which can result in wafer warp, as well as cracks, bubbles, foreign particles or segregation zones and internal interfaces.Type: GrantFiled: July 31, 1986Date of Patent: May 3, 1988Assignee: General Electric CompanyInventor: Walther Rehwald
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Patent number: 4735917Abstract: A process for forming a silicon-on-sapphire integrated circuit comprises forming a layer of a conformal dielectric material, such as silicon dioxide, over a sapphire substrate having at least one island of silicon on a major surface thereof; forming a layer of a planarizing material over the dielectric layer, anisotropically etching the planarizing material for a time sufficient to expose the surface of the dielectric layer overlying the island; etching the dielectric layer for a time sufficient to expose at least the top surface of the island; removing the remaining planarizing material, growing a thin layer of gate oxide on the exposed surface of the island and providing a patterned layer of conductive polycrystalline silicon thereover. The etching of the dielectric layer can be continued to at least partially expose the sidewall surface of the islands.Type: GrantFiled: April 28, 1986Date of Patent: April 5, 1988Assignee: General Electric CompanyInventors: Doris W. Flatley, Kenneth M. Schlesier
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Patent number: 4731155Abstract: A process is provided for forming a patterned layer of a polymeric material on a substrate for the lithographic processing thereof. A layer of polymeric material is formed on the substrate, embossed to form a pattern of peaks and valleys and dry etched to remove the residual polymeric material in the valleys, thereby exposing a portion of the substrate surface.Type: GrantFiled: April 15, 1987Date of Patent: March 15, 1988Assignee: General Electric CompanyInventors: Louis S. Napoli, John P. Russell
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Patent number: 4712126Abstract: A low resistance silicon conductor for tunnelling under an intervening metal conductor on a semiconductor device is provided. The low resistance conductor includes two layers of highly doped single crystalline or polycrystalline silicon which are stacked so that one is directly over the other. A pair of metal conductors are arranged, one on each side of the intervening metal conductor. Each of the pair of metal conductors is formed in ohmic contact with a portion of each of the two layers of silicon near one of their adjacent edges, thereby forming a two layer conductive tunnel under the intervening metal conductor.Type: GrantFiled: March 17, 1986Date of Patent: December 8, 1987Assignee: RCA CorporationInventor: Francis R. Slattery
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Patent number: 4704186Abstract: A plurality of first cavities is formed in the planar surface of a silicon substrate. A first oxide region of predetermined thickness is formed in each of the first cavities such that each of the first oxide regions has a surface which is coplanar with the substrate surface. A layer of monocrystalline silicon is then epitaxially deposited over the planar first oxide region/substrate surface. Second cavities are then formed through the monocrystalline silicon layer and into the substrate adjacent the first oxide regions, extending to a depth equal to approximately one-half that of the first oxide regions. The second cavities are then thermally oxidized so as to form second oxide regions therein, these second oxide regions being coplanar with the first oxide regions. Silicon is next epitaxially deposited on those portions of the monocrystalline silicon layer remaining on the first oxide regions so as to yield a continuous monocrystalline silicon sheet over the first and second oxide regions.Type: GrantFiled: February 19, 1986Date of Patent: November 3, 1987Assignee: RCA CorporationInventor: Lubomir L. Jastrzebski
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Patent number: 4702993Abstract: An improved electron beam resist structure comprises an organic planarizing layer which has been treated with an ion beam for a time sufficient to render it conductive and an electron beam resist layer thereover. The electron beam resist layer is preferably oxygen plasma resistant. When the resist layer is not resistant to oxygen plasma and it is desired to develop the planarizing layer by oxygen plasma, the structure additionally includes a thin hard mask layer, suitably of silicon dioxide, interposed between the conductive planarizing layer and the resist layer.Type: GrantFiled: November 25, 1985Date of Patent: October 27, 1987Assignee: RCA CorporationInventors: Lawrence K. White, Richard Brown
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Patent number: 4687537Abstract: A process of forming an epitaxial metal silicide layer on a silicon substrate is disclosed. A thin layer of a first metal that will form an oxide in preference to silicon is initially deposited on the substrate. A preferred first metal is titanium. A layer of palladium, platinum or iridium is deposited thereover. An exceptionally uniform, conductive layer of metal silicide is thereby formed by epitaxial growth without the necessity of a high temperature anneal. The disclosed process is particularly useful in forming ultra thin metal silicide Schottky barriers in devices such as infrared imaging arrays.Type: GrantFiled: April 15, 1986Date of Patent: August 18, 1987Assignee: RCA CorporationInventors: Dorothy M. Hoffman, Frederick J. Tams, III, Joseph T. McGinn
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Patent number: 4675984Abstract: A method of exposing only the top surface of a narrow mesa is disclosed wherein a protective layer may be very precisely formed on a very narrow mesa for subsequent doping of areas adjacent the mesa without doping the mesa itself. A variation of the invention includes forming an opening directly over the narrow mesa so that a contact may be made at only the top surface of the mesa or the upper portion of the mesa may be doped independent of surfaces adjacent the mesa.Type: GrantFiled: September 19, 1985Date of Patent: June 30, 1987Assignee: RCA CorporationInventor: Sheng T. Hsu
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Patent number: 4674224Abstract: A fishing lure is disclosed having the capability of being selectively operable between a plurality of different modes of operation. For example, the lure may be arranged to remain on the surface of the water while trolling or it may be arranged to dive below the surface. The body of the lure is of one piece unitary construction having a selectively positionable band or ring captive about its approximate midpoint. An angled deflecting surface is formed on the front of the lure and cooperates with the onrushing water and the weight of the hook which is attached to the movable ring to determine the mode of operation. By selectively moving the ring, and thereby the hook, to one position or another with respect to the deflecting surface, the lure will be made to remain on the surface of the water, dive below the surface, or move to one side or the other with respect to the path of travel of the trolling boat.Type: GrantFiled: April 11, 1986Date of Patent: June 23, 1987Inventor: Robert Williams
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Patent number: 4675225Abstract: A thermal insulating blanket is disclosed for providing an insulating barrier across doorways, stairways, and other openings between a heated area and an unheated area. The thermal insulating blanket includes an inner layer of flexible and compressible insulating material and an outer layer of flexible material. Means is provided for venting the air contained within the thermal insulating blanket to the ambient atmosphere when the blanket is compressed and restrained for compact storage. A resiliency inherent in the structure assures that the blanket returns to its pre-compressed state upon release of the restraints.Type: GrantFiled: April 5, 1985Date of Patent: June 23, 1987Assignee: J.M.J. Technologies Inc.Inventor: William P. Cutler
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Patent number: 4660276Abstract: A method for making a MOS field effect transistor structure having tungsten silicide contact surfaces for the gate and source and drain regions is disclosed. Protective oxide is very precisely positioned so that a tungsten layer is formed on only selected silicon surfaces by selective deposition. Next, a layer of polysilicon is formed on said tungsten layer. The resulting structure is treated in an oxygen atmosphere to form the desired tungsten silicide. A silicon nitride cap can also be used to cover the gate portion during source and drain formation.Type: GrantFiled: August 12, 1985Date of Patent: April 28, 1987Assignee: RCA CorporationInventor: Sheng T. Hsu
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Patent number: 4656055Abstract: A three part edge seal for an integrated circuit semiconductor chip is disclosed. The edge seal includes two separate layers of metal one of which overlays the other in electrical contact. One of the metal layers is in ohmic contact with a highly doped region formed in the planar surface of the semiconductor body. The two metal layers serve as an electrical conductor to distribute power to various portions of the integrated circuit contained in the chip and electrically charge the highly doped region to prevent migration of ions into the active areas of the integrated circuits.Type: GrantFiled: April 18, 1986Date of Patent: April 7, 1987Assignee: RCA CorporationInventor: Robert A. Dwyer
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Patent number: 4651178Abstract: A zener diode structure for integrated circuits is disclosed. The device includes a pair of opposing zener diodes separated by a parasitic resistance. The zener breakdown junctions of the two diodes are well below the surface of the device thereby reducing any adverse effect of stray surface charges and ultraviolet radiation. Further, the doping levels of the opposing diodes are selected to reduce drift in the breakdown voltage due to variations in operating temperature of the device.Type: GrantFiled: May 31, 1985Date of Patent: March 17, 1987Assignee: RCA CorporationInventor: Leslie R. Avery
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Patent number: 4631562Abstract: A zener diode structure for integrated circuits is disclosed. The device includes a pair of parallel zener diodes connected back to back with a third zener diode. The anode of one of the parallel diodes is connected to the anodes of the other two diodes through a parasitic resistance. The zener breakdown junctions of two of the diodes are well below the surface of the device thereby reducing any adverse affect of stray surface charges and ultraviolet radiation. Further, the doping levels of the opposing diodes are selected to reduce drift in the breakdown voltage due to variations in operating temperature of the device.Type: GrantFiled: May 31, 1985Date of Patent: December 23, 1986Assignee: RCA CorporationInventor: Leslie R. Avery
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Patent number: 4614294Abstract: An apparatus for holding an IC device for tinning the leads in a wave soldering machine is disclosed. The apparatus utilizes a pair of beveled surfaces, one on each side of the lead to be tinned, to limit the extent of penetration of the lead into the molten solder. The beveled surfaces are made of a material which cannot be wet by the molten solder, therefore, surface tension of the solder will tend to limit penetration of the molten solder into the area defined by the beveled surfaces.Type: GrantFiled: October 29, 1985Date of Patent: September 30, 1986Assignee: RCA CorporationInventor: Charles A. Weaver
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Patent number: 4609187Abstract: An apparatus for rapidly and accurately positioning and holding a very small elongated body, such as a stylus holder during manufacturing is disclosed. A pair of magnets or magnetized regions are utilized to position the stylus holder both rotationally and axially. A pusher mechanism, in conjunction with a pair of locating blocks very precisely aligns the stylus holder, causing it to engage the seat of an anvil for support during the manufacturing operation. A retaining mechanism retains the stylus holder within the apparatus until completion.Type: GrantFiled: August 2, 1984Date of Patent: September 2, 1986Assignee: RCA CorporationInventor: David W. Fairbanks