Abstract: An integrated circuit is shown in which provision is made for terminating or locking out the operating circuitry when the supply voltage has fallen below a level that can cause anomalous or unreliable operation. Certain selected transistors are provided with saturation sensors which operate to produce a current when the transistors go into collector saturation. When any of the sensors indicates the onset of saturation, clamping circuitry is energized to provide lock out. In addition, a temperature compensated dummy bandgap circuit is included to sense extremely low supply voltages and provide the lockout function under conditions where a reliable saturation indication might not be available.

Abstract: A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time.

Abstract: An RGB video display terminal (VDT) is disclosed and the color cathode ray tube (CRT) driver circuits detailed. The driver circuits include a common video gain control which can be varied over a wide range without changing the DC bias level. Each CRT gun can have its driver gain separately controlled over a vernier range and its DC bias can be separately controlled. The video amplifier is AC coupled to the video input and includes a DC reinsertion circuit which clamps the DC bias at a level related to the composite video level immediately following the sync pulse. Therefore, the DC reinsertion is clamped for each scanning line at the CRT black level. The video amplifier also includes a blanking circuit which turns the CRT guns off during the VDT retrace interval. Thus, the driver circuits can drive the CRT guns in a manner that will simultaneously control their operation for the color display and yet take into account the manufacturing tolerance in individual gun characteristics.

Abstract: An anti-noise circuit dissipates parasitic tank circuit energy which causes ground unershoot and V.sub.cc overshoot in the power rails (PG,PV) of an integrated circuit device. An anti-noise circuit transistor element, either an anti-undershoot circuit transistor element (AUCT) or an anti-overshoot circuit transistor element (AOCT) incorporates selected resistance in its primary current path for providing dissipating resistance. The anti-noise circuit couples a current source (PV), the anti-noise circuit transistor element (AUCT, AOCT) with dissipating resistance, and power rail parasitic lead inductance in series in a sacrificial current path. A control circuit coupled to the control node of the anti-noise circuit transistor element (AUCT,AOCT) causes sacrificial current flow following switching of potential levels at the output for dissipating parasitic tank circuit energy. The control circuit incorporates an active pullup and pulldown passgate (RST1,ICT1,OCT1) (RST2,ICT3, OCT2) between the data input (V.

Abstract: An ECL to TTL translator circuit incorporates an ECL input gate, a TTL output gate, and a voltage amplifier transistor element circuit coupled between the ECL input gate and TTL output gate for effecting the translation. The ECL gate has differential ECL inputs for receiving ECL input signals at least at one of the ECL inputs (V.sub.IN) and differential first and second ECL output nodes (A, B). First and second emitter follower output circuits (Q7, Q3) are coupled to the respective first and second ECL output nodes (A, B). The TTL gate (12) has a TTL output (V.sub.OUT) for delivering TTL output signals corresponding to ECL input signals. The TTL gate phase splitter transistor element (Q9) controls the TTL output (V.sub.OUT). The collector node of a voltage amplifier transistor element (Q6) is coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element.

Abstract: A pin electronics test circuit applies test signals at a pin of an ECL integrated circuit (IC) device under test (DUT) and senses and measures pin signals received from a pin of the DUT. The pin electronics test circuit incorporates test signal first and second electrical paths (TL1, TL2) (TL11, TL12) with respective test connect and disconnect first and second nodes (n1)(n2). First and second termination circuits (RL1, A1)(RL2,A2), first and second DC test signal generators (A1 etc.) (A2 etc.) for forcing DC test signal voltages and currents, AC test signal generator (I.sub.HI, I.sub.LO etc.) for switching between and driving AC test signals of high and low potential levels, and pin signal sensing and measuring circuits (CR1, 8CR2) are all contained on a single pin electronics card (PEC) (54) or formed as a single unit for a pin or complementary pair of pins of the DUT.

Abstract: An electrical connector (10) provides a mechanical coupling and an electrical interface between circuit boards (12,14). An elastomeric electrical conductor (20) provides compressible electrical connector paths between first and second sets of electrical contact pads (28,15) coupled to the respective circuit boards. A compression mounting assembly (22) aligns and retains the elastomeric electrical conductor (20) between the sets of electrical contact pads. The elastomeric electrical conductor (20) affords relatively high frequency signal conducting paths with substantially constant impedance for example for passing test signals and pin signals without distortion between circuit boards in the test head of an IC device tester. A mechanical spring system (64,65) spring loads the compression mounting assembly (22) and provides a relatively high mechanical compliance coupling between circuit boards (12,14) to accommodate relative change of position of the boards due to misalignment or board warpage.

Abstract: TTL to CMOS level translating buffer circuits incorporate multiple stages with feedback and forward couplings between stages that eliminate static current I.sub.cct when TTL high potential level data signal is applied at the buffer circuit input. The feedback and feed forward couplings maintain and enhance signal propagation speed in the buffer circuits at the same time. TTL to CMOS translating latch circuits and flip-flop circuits similarly incorporate feedback and feed forward circuit couplings to save and retain data signals during latch mode, static mode, and tristate mode operation while at the same time substantially eliminating static high current I.sub.cct. The clock circuit portions for the latch and flip-flop circuits also are arranged in clock circuit configurations that are free of static current I.sub.cct.

Abstract: A circuit capable of being integrated into a self-isolated DMOST is driven by a sense resistor that is created from the DMOST drain metallization. The circuit produces an output current that is ratioed with respect to the DMOST current with the ratio being determined by the value of a single resistor. The output current is sourced when the DMOST conducts its source current and the output current is sunk when the DMOST shunt diode conducts. Thus, the circuit not only produces a DMOST current related output it also distinguishes the mode of DMOST conduction.

Abstract: An output buffer circuit reduces switching induced noise in integrated circuit devices. A pulldown feed forward circuit is coupled between the input and the output pulldown transistor. The pulldown feed forward circuit bypasses at least some of the intermediate circuit elements of the output buffer circuit. The pulldown feed forward circuit initiates a relatively small sinking current through the output pulldown transistor in response to a first signal at the input before the intermediate circuit elements initiate relatively large sinking current through the output pulldown transistor means. A pullup feed forward circuit is coupled between the input and the output pullup transistor means. The pullup feed forward circuit bypasses at least some of the intermediate circuit elements of the output buffer circuit.

Abstract: A post-assembly trim of a monolithic IC is set forth wherein selected package pins can be employed to address the on-chip trim circuit. Then, after the trim is completed, the circuit is addressed to provide a disconnect of the coupling between the trim pins and the post assembly trim circuit of the IC, while leaving the pins fully usable for other purposes. This means that following the post-assembly trim the trim pins cannot accidentally be employed for further trimming and the packaged IC is user-proof. A circuit that employs zener zapping for both trimming and disconnect is detailed and the invention is clearly usable for plastic encapsulated devices. However, when cavity containing packages are involved it is shown that a combination of zener zapping and fuse blowing can be employed.

Abstract: The present invention provides an ECL to CMOS level translation circuit which uses a dynamic, internally generated reference voltage to translate ECL level signals into CMOS level signals. The translator includes an input translation circuit which uses emitter-follower bipolar transistors for receiving and interpreting the ECL level signals and to generate the dynamic, internally generated reference potential, and an output circuit for outputting the CMOS signals.

Abstract: An automotive voltage regulator is disclosed to have plural regulated outputs using a transient protected isolator output stage (TPIOS) that prevents a system fault condition on any one output from adversely affecting the other outputs. In an automotive environment employing a nominal 14-volt supply, an individual output can be taken from -4 to +26 volts without causing damage or having any significant reaction on the non-faulted outputs. The circuit employs a relatively small NPN output pass transistor and, therefore, requires a relatively low value stabilizing bypass capacitor.

Abstract: To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe.

Abstract: Intermediate path splitting circuit arrangements are coupled between the input node and output stage of an IC defining a plurality of different signal propagation paths. A relatively higher speed output pullup turn on signal progagation path is coupled between the input node and the output pullup transistor element for turning on the output pullup transistor element at relatively higher speed in response to a first input data signal. A relatively slower speed output pulldown turn off signal propagation path turns off the output pulldown transistor element at a relatively slower speed in response to the first data input signal. Similar circuit arrangements are provided for relatively high speed turn on of the pulldown transistor element and relatively low speed turn off of the pullup transistor element. Control of turn on and turn off of the respective output pullup and pulldown transistor elements is from separate output driver nodes for higher speed operation.

Abstract: A semiconductor device inspection template for use in visual inspection of semiconductor die or packages includes a selectively patterned transparent film mounted in a sleeve adapted for rapid placement and removal from an optical inspection instrument's optical tube.

Abstract: A gauge circuit for use with a wide angle air core meter display having high linearity and adapted for use with a remote sensing resistor. A constant sense current is provided and its value is moudlated at a frequency that is high with respect to the frequencies associated with offset voltages that occur with a sense resistor that is grounded remotely from the gauge ground. A low duty cycle pulse modulation shape is disclosed for the purpose of minimizing electromagnetic interference radiation.

Abstract: A trim arrangement for adjusting a differential input stage in a BIFET.RTM. integrated circuit is presented wherein the trimming is done at wafer probing in the manufacturing process. Trim JFETs are invoked by means of reverse biased zener diodes which can be zapped thereby to achieve trimming in the conventional manner. The trim JFETs are ratioed in size so that the trim is V.sub.P compensated over a relatively broad range. An improved trim structure is presented wherein the offset trim is V.sub.P compensated and operated in a manner that renders its effect on the circuit constant and independent of the conventional load trim.

Abstract: Current mode logic configuration circuits are shown for use with linear integrated circuit chips. The circuits employ plural collector lateral transistors to provide logic current source outputs in response to logic current inputs that are accepted by NPN transistor current mirrors acting as current sinks. Conventional logic functions are detailed and a toggle flip-flop configuration is shown being composed of the basic logic gates. Since the disclosed current mode voltage swings are small the circuit speed is relatively high at a given shunt capacitance. Die surface area is low with many transistors sharing common n-epitaxial tubs.

Abstract: A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node of an emitter follower transistor element is coupled to a collector node of the input transistor circuit in an inverting coupling. The emitter node is coupled to a base node of the phase splitter transistor element for sourcing base driven current to the phase splitter transistor element in response to data signals at the input. The emitter follower provides transient "overdrive" for fast turn on of the phase splitter. A first clamp circuit between the base node of the emitter follower transistor element and the low potential power rail clamps the base node at a low potential level when the emitter follower transistor element is relatively non-conducting and establishes the input threshold voltage level.