Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

Abstract: A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., deep UV lithography). The BARC layer (30) is etched with an etch chemistry of HBr/O2 using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).

Abstract: An integrated circuit comprises a dielectric layer disposed outwardly from a semiconductor substrate, the dielectric layer comprising at least one cavity having sidewalls extending from an outer surface of the dielectric layer inwardly toward the substrate. The integrated circuit further comprises a contaminant resistant barrier disposed outwardly from at least the sidewalls of the cavity in the dielectric layer.