Abstract: A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.

Abstract: Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to memory cells that drive the gates of the transistors, memory cells that drive the sources of the transistors, and level shifters that drive the gates of the transistors. In these techniques, an appropriate gate to source voltage (VGS) can be applied to a transistor in its off state. Of importance, this VGS can under-drive the transistor, which significantly reduces the sub-threshold leakage of that transistor. These techniques fail to affect a transistor in its on state, thereby ensuring that high speed performance of the integrated circuit can be maintained.

Abstract: A method of programming a programmable logic device (PLD) includes identifying and reading an identification code on the PLD. At this point, a plurality of check bits can be generated based on the identification code. These check bits can be used to correct any errant bits in the identification code at a subsequent point in time. A first key is then created using the identification code. The configuration bitstream is encrypted using the first key. The encrypted bitstream and the check bits are then stored for subsequent use. To program the PLD, the stored check bits are transmitted to the PLD and used to correct any errant bits in the identification code at that point in time. A second key is then created using the corrected identification code. The encrypted configuration bitstream is then transmitted to the PLD and decrypted using the second key.

Abstract: A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD.

Abstract: Battery management can be advantageously integrated into a programmable logic device (PLD). Specifically, by using a programmable battery controller provided on the PLD, the user can make a decision regarding battery choice much later in the design process, reduce the inventory of batteries associated with the system/product, increase the life of the batteries, and upgrade to the newest technology battery at the user's discretion. The battery controller can be implemented on any type of PLD, e.g., an FPGA, potentially requiring battery management for critical circuits.

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

Abstract: A method for programming a semiconductor element in a semiconductor structure such as an IC involves reducing the backside thickness of the substrate and directing an energy beam through the backside at an opaque component of the semiconductor element. A support structure mounted on the semiconductor structure provides support during and after the thinning operation. Alternatively, the substrate can be thinned only under the semiconductor element, leaving the rest of the substrate thick enough to maintain structural integrity. The energy beam heats the opaque component. The prior thinning operation minimizes heat dissipation away from the semiconductor element, so that dopant diffusion occurs, changing the electrical characteristics of the semiconductor element. By modifying selected elements in this manner, a semiconductor structure can be permanently programmed, even if it does not include non-volatile memory. Additionally, security is enhanced since the programming leaves no visible signs.

Abstract: An integrated circuit (I/C) assembly includes a dedicated voltage sensor line for determining with a high degree of accuracy the operating voltage at a predetermined sensor point on the IC die. The dedicated voltage sensor line connects the sensor point to an input/output (I/O) structure of the IC die, which in turn is connected to a voltage sense pin on the package of the IC assembly. In this manner, an end user can accurately monitor the operating voltage at the voltage sensor point on the IC. Additionally, an end user can connect a control circuit to the voltage sensor pin to control either the supply voltage or secondary parameters.

Abstract: An accurate, cost-effective system and method for correcting 3D effects on an alternating phase-shifting mask (PSM) is provided. To facilitate this correction, a library can be built to include a first group of 180 degree phase-shifting regions, wherein these regions have a common first size. Based on this first size, 3D simulation is performed. A transmission and a phase are altered in a 2D simulation based on this first size until a shape dependent transmission and a shape dependent phase allow the 2D simulation to substantially match the 3D simulation. Finally, a modified first size is chosen using the shape dependent transmission and the shape dependent phase such that a 2D simulation based on the modified first size substantially matches the 3D simulation based on the first size. The library associates the first size with the modified first size, the shape dependent transmission, and the shape dependent phase.

Abstract: A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

Abstract: A charge pump system and method including a charge pump and a pulse width modulated (PWM) controller are provided. The charge pump includes a pump capacitor, a reservoir capacitor, and pump circuitry. During a first phase, the pump circuit couples the pump capacitor between a first supply voltage and a second supply voltage. During a second phase, the pump circuit couples the pump capacitor and the reservoir capacitor in series between the first supply voltage and an output terminal of the charge pump system. The PWM controller, which is coupled to the pump circuitry, determines the phase of the charge pump.

Abstract: The device and method that receives a signal from a first interface operating at a data rate. An extraction component extracts information from the signal to produce an information signal having a frequency distinct from the data rate of the first interface. A first receive clock component receives a first clock signal that has a frequency equal to a frequency of a second interface. A synchronizer component synchronizes the information signal through utilization of the first clock signal to the frequency of the second interface.

Abstract: A method for providing licenses to client computer systems to allow the client computer systems to use licensed software products includes receiving a request for a feature license for a feature included in a package, filtering the request based on whether the license requires the checkout of a parent license, granting a package license to the client computer system when the client computer system is allowed to receive the package license according to a license policy and denying the package license to the client computer system when the client computer system is not allowed to receive the package license according to the license policy. The request may include checkout data that includes at least one desired feature attribute.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

Abstract: A computer implemented method of producing a reduced order model of an electronic circuit to model the connection of two or more circuits. Arnoldi reduced order models for nodes of circuits to be interconnected may be computed. A set of modified nodal analysis matrices for the combination of the two circuits may be constructed. A rank one update may be applied to the modified set of nodal analysis matrices to produce a reduced order model of the combined electronic circuits. In this novel manner, a reduced order model for a combination of circuits may be produced from the individual reduced order models of the individual circuits without the need to recompute the reduced order models of the original circuits, and without the need of the original parasitic network models. The resulting reduced order model may be used in a variety ways consistent with well known uses of such matrices within the field of electronic design automation.

Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.

Abstract: A method and system is provided for synchronizing data between an application layer having a first clock speed and a circuit having a second clock speed. The first clock speed generally being faster than the second clock speed. The second clock speed typically being determined by an appropriate standard. Data and a function opcode representative of a computation to be performed on at least a portion of the data, is received at a synchronizing element from the application layer. The synchronizing element may be a first in first out type device. The data and its associated function opcodes are stored by the synchronizing element until transmitted to a circuit in accordance with the second clock speed. A compute logic in the circuit performs a computation on at least a portion of the data based on the associated function opcode. A system is also provided for synchronizing data between an application layer and a logic circuit. The system may be advantageously employed in audio/visual applications.

Abstract: The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates.

Abstract: Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a non-critical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this non-critical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

Abstract: A system and a method for performing circuit simulation on a integrated circuit design that is represented by a hierarchical netlist. The system and method utilize, in one embodiment, an event driven simulator that divides or “cuts” along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into their Thevenin equivalents. Once a Thevenin equivalent is computed, matrix computations are used to compute the cut node voltages and sensitivity vectors may be used to then determine the internal node voltages. This is done for each event. In the event driven example, a group of leaf cells are identified that are touched by a given event. This group is then cut based on the hierarchical boundaries of the input netlist. The system maintains dynamic node voltages across the entire netlist and also maintains instance specific dynamic information for each cell.