Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.

Abstract: Methods, apparatus and machine readable medium are described in which BIOS initialization code divides one or more storage devices into two or more portions. Further, a BIOS device handler may use the portions of the divided storage devices to implement a storage array that provides attributes of one or more RAID levels.

Abstract: A processor-based device (e.g., a wireless device) may include a processor and a semiconductor memory (e.g., a flash memory) to selectively pipeline and prefetch memory data, such as executable data, in one embodiment, using prefetch/pipeline logic that may enable storage of a first indication associated with executable data at a first storage location and a second indication associated with executable data at a second storage location. Upon retrieval, the prefetch/pipeline logic may selectively perform at least one of pipelining and prefetching of the executable data associated with the second storage location based on the first indication.

Abstract: A computing device maintains coherency while supporting addition and removal of memory caching agents without rebooting the computing device.

Abstract: An apparatus and method for selectively loading and enabling software stored within firmware of an electronic device to support an input device coupled to the electronic device if a power switch is pressed and held for at least a predetermined period of time as the power switch is used to turn the electronic device on.

Abstract: Machine-readable media, methods, and apparatus are described to monitor and throttle issuance of transactions. In some embodiments, transactions are monitored during a monitoring window based upon cycle type. In response to determining that a threshold has been exceeded during the monitoring window, issuance of transactions during a throttling window are limited to a budget. Further, transactions issued during the throttling window consume a portion of the budget that based upon their cycle type.

Abstract: Methods, apparatus and computer readable medium are described that attempt increase trust in a system time provided by a system clock. In some embodiments, a detector detects activities that may be associated with attacks against the system clock. Based upon whether the detector detects a possible attack against the system clock, the computing device may determine whether or not to trust the system time provided by the system clock.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a memory controller of a processor and/or chipset may adaptively determine whether to close pages of a memory in an attempt to increase perceived memory performance.

Abstract: A double gate MOSFET having a control gate and a signal gate. The effective threshold voltage seen by the signal gate may be modified by charging the control gate. The effective threshold voltage may be increased in magnitude to reduce sub-threshold leakage current when the double gate MOSFET is inactive. When inactive, the control gate is maintained at a negative voltage for a double gate nMOSFET, and is maintained at a positive voltage for a double gate pMOSFET. When active, the control gate is charged to a voltage close to the threshold voltage, and then floated, so that a signal voltage applied to the signal gate may turn the double gate MOSFET ON during a signal voltage transition via the coupling capacitance between the signal and control gates.

Abstract: A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.

Abstract: Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

Abstract: A cooling system hinge mounted to a portion of an enclosure of an electronic system to which a cooling device may be releasably and pivotably attached in at least an open position to permit access to components within the electronic system and a closed position to permit installation of a cover to close the enclosure.

Abstract: A method and an apparatus for releasably retaining a heatsink in contact with an IC attached to a circuitboard in which the heatsink is inserted into a spring cage that is pivotally connected with an actuation lever, wherein at least a pair of spring tabs engage the heatsink to press a thermal conductive surface of the heatsink towards a circuitboard and an IC attached to the circuitboard when the combination of the heatsink, actuation lever and spring cage are inserted into the rectangular frame of a retention module mounted on the circuitboard so as to surround the IC and the lever portion of the actuation lever is pivoted towards the spring cage so as to cause retention points on the actuator portions of the actuation lever and on the rectangular frame of the spring cage to engage corresponding retention points on the rectangular frame of the retention module.

Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Abstract: A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

Abstract: Briefly, in accordance with one embodiment of the invention, a computing system includes an event programming interface and a management application. The management application is communicatively coupled to the event programming interface so that the management application may register an event that the event programming interface will notify the management application once that event has occurred. In one embodiment, the event programming interface may notify the management application of the occurrence of an event that is associated with a storage medium in a RAID process.

Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.

Abstract: A circuit to provide a differential signal output in response to a single-ended signal input, the circuit allowing for a wide common-mode input signal by providing complementary amplifier structures.

Abstract: A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.

Abstract: Text and graphics elements may be alpha blended in a way to reduce flicker when the text or graphics are display by a processor-based television receiver. The alpha values are used to intelligently smooth pixels adjacent the element to create television text and graphics.