Abstract: A virtual machine (VM) runs on system hardware, which includes a physical network interface device that enables transfer of packets between the VM and a destination over a network. A virtual machine monitor (VMM) exports a hardware interface to the VM and runs on a kernel, which forms a system software layer between the VMM and the system hardware. Pending packets (both transmit and receive) issued by the VM are stored in a memory region that is shared by, that is, addressable by, the VM, the VMM, and the kernel. Rather than always transferring each packet as it is issued, packets are clustered in the shared memory region until a trigger event occurs, whereupon the cluster of packets is passed as a group to the physical network interface device.

Abstract: I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. Because the VMM, and thus the transformation operation, is transparent to the VM, the transformation cannot be prevented or undone or even affected by any action by a user of the VM. Examples of the non-defeatable transformation of I/O data include generating display overlays such as banners, masking out portions of a display, encryption, compression and network shaping such as bandwidth limiting.

Abstract: Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.

Abstract: Computer-executable instructions in a computer are verified dynamically, after they have been identified for submission for execution, but before they are actually executed. In particular, for at least one current instruction that has been identified for submission to the processor for execution, an identifying value, for example, a hash value, is determined for a current memory block that contains the current instruction. The identifying value of the current memory block is then compared with a set of reference values. If the identifying value satisfies a validation condition, then execution of the current instruction by the processor is allowed. If the validation condition is not satisfied, then a response is generated: In the common case, execution of the current instruction is not allowed, or some other predetermined measure is taken.

Abstract: Upon occurrence of a trigger condition, writes of allocation units of data (including code) to a device, such as writes of blocks to a disk, are first encrypted. Each allocation unit is preferably a predetermined integral multiple number of minimum I/O units. A data structure is marked to indicate which units are encrypted. Upon reads from the device, only those allocation units marked as encrypted are decrypted. The disk protected by selective encryption is preferably the virtual disk of a virtual machine (VM). The trigger condition is preferably either that the virtual disk has been initialized or that the VM has been powered on. Mechanisms are also provided for selectively declassifying (storing in unencrypted form) already-encrypted, stored data, and for determining which data units represent public, general-use data units that do not need to be encrypted. The “encrypt-on-write” feature of the invention may be used in conjunction with a “copy-on-write” technique.

Abstract: A lighting system has an array (100) of at least one light-emitting solid-state element such as a light-emitting diode (LED) or a laser diode. A voltage source (10), which may supply either alternating or direct current, energizes the array. Array state circuitry (125; Q2, R2), electrically connected in series with the array (100), senses at least one state of the array, such as the amount of current passing through the array, or temperature. Secondary circuitry (127; R1, Q1; 200, 201, 202; 200, R4, Q1; 126, 127) is connected in parallel with the array (100). A switching component (Q1; Q1, Q3; 202) adjusts the current passing through the secondary circuitry in accordance with the sensed state of the array such that current through the array is maintained substantially constant.

Abstract: An ultrasound transducer includes an array of PZT elements mounted on a non-recessed distal surface of a backing block. Between each element and the backing block is a conductive region formed as a portion of a metallic layer sputtered onto the distal surface. Traces on a longitudinally extending circuit board—preferably, a substantially rigid printed circuit board, which may be embedded within the block—connect the conductive region, and thus the PZT element, with any conventional external ultrasound imaging system. A substantially “T” or “inverted-L” shaped electrode is thereby formed for each element, with no need for soldering. At least one longitudinally extending metallic member mounted on a respective lateral surface of the backing block forms a heat sink and a common electrical ground. A thermally and electrically conductive layer, such as of foil, transfers heat from at least one matching layer mounted on the elements to the metallic member.

Abstract: A thread scheduling mechanism is provided that flexibly enforces performance isolation of multiple threads to alleviate the effect of anti-cooperative execution behavior with respect to a shared resource, for example, hoarding a cache or pipeline, using the hardware capabilities of simultaneous multi-threaded (SMT) or multi-core processors. Given a plurality of threads running on at least two processors in at least one functional processor group, the occurrence of a rescheduling condition indicating anti-cooperative execution behavior is sensed, and, if present, at least one of the threads is rescheduled such that the first and second threads no longer execute in the same functional processor group at the same time.

Abstract: One embodiment is a method for transferring data packets from a virtual computer having a virtual network interface device to a destination over a network, the method includes: (a) storing two or more guest address pointers associated with the data packets in a guest network transmission queue prior to handling the data packets; (b) the virtual network interface device converting the two or more guest address pointers to physical address pointers, and storing the physical address pointers in a physical network transmission queue; and (c) transferring the data packets from the virtual machine of the virtual computer over the network via a physical network interface device based on the physical address pointers in the physical network transmission queue.

Abstract: Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.

Abstract: A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the return address after any IL call to a subroutine at a target entry address P, the corresponding OL return address is stored in an array at a location determined by an index calculated as a function of P. After completion of execution of the OL translation of the IL subroutine, execution is transferred to the address stored in the array at the location where the OL return address was previously stored. A confirm instruction block is included in each OL call site to determine whether the transfer was to the correct or incorrect call site, and a back-up routine is included to handle the cases of incorrect call sites.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: One or more parameters, such as time, are reported to a center using a form. The center then automatically extracts data from the form and converts it for storage and subsequent processing or review. The form is preferably a tangible form, which the sender completes, and then faxes or emails to the center. Image capture, registration, and feature recognition routines are included to enable the center to extract the reported data with no need for data reentry or human intervention. The invention is particularly suitable for remote employees who need to submit time sheets, expense reports, and the like to an employer, or for automatic analysis of submitted inventory reports, product orders, etc.

Abstract: Assembly to separate out liquid frotfi a multiphase fluid flow, comprising a scrubber, a column, a separator or other conventional separation equipment, combined with a deliquidizer that is connected as a preseparator to the fluid inlet. in that the deliquidizer functions according to a cyclone principle. With the assembly according to the invention the deliquidizer is modified such that it can be combined with conventional separation equipment such that a surprising improved technical effect is achieved. More specific the improved technical effect is achieved for assemblies where the deliquidizer is vertically oriented placed outside conventional separation equipment, with main flow direction upwards or downwards, or with the deliquidizer placed within conventional separation equipment.

Abstract: A current set of user-selectable choices is associated with a displayed graphical input device, which is used to select a value of an input parameter. Each user-selectable choice has at least one pair of information fields separated by a delimiter and each information field comprises sequentially ordered characters. A search for a matching entry to assign to the input parameter is carried out as the user enters each of a sequence of characters, and if a match is not found in a first information field, then (or simultaneously) it is sought in a different information field, also on the basis of the character-by-character user entries.

Abstract: Seabed located storage for crude oil or other fluid, distinguished in that it is comprising a storage section in form of an oil and waterproof cloth formed as a flexible balloon that can be filled with, store and emptied for a storage fluid, a structure section formed as an external casing over the storage section, which structure section is closed in the upper part such that an upward close volume of size at least corresponding to the volume of the storage section is formed, but with openings to the surroundings in the lower part, an anchoring section formed as a substructure between the structure section and the seabed, with means for anchoring to or stable placement on the seabed, and a transfer section comprising pipes and valves for loading and unloading of a storage fluid, arranged in substance exterior to the upper part of the storage.

Abstract: A printer circuit board for mounting electrical components such as LEDs has outward edge protrusion on which an electrically conductive material is deposited such that the board itself can be used to make electrical contact in a pre-existing, commercially available fitting, such as a screw-in or base fitting designed to receive incandescent light bulbs. For a screw-in fitting the board can optionally be made slightly wider than the inner diameter of the fitting but be provided with at least one axially extending slit; the board is then compressed slightly but biased outward to provide better electrical contact when inserted into fitting.

Abstract: At least one guest system, for example, a virtual machine, is connected to a host system, which includes a system resource such as system machine memory. Each guest system includes a guest operating system (OS). A resource requesting mechanism, preferably a driver, is installed within each guest OS and communicates with a resource scheduler included within the host system. If the host system needs any one the guest systems to relinquish some of the system resource it currently is allocated, then the resource scheduler instructs the driver within that guest system's OS to reserve more of the resource, using the guest OS's own, native resource allocation mechanisms. The driver thus frees this resource for use by the host, since the driver does not itself actually need the requested amount of the resource. The driver in each guest OS thus acts as a hollow “balloon” to “inflate” or “deflate,” that is, reserve more or less of the system resource via the corresponding guest OS.

Abstract: In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is determined which portions of the cache are utilized by the observed process. Utilization of the cache is optimized based on result of the determination of which portions of the cache are utilized by the observed process.