Abstract: A method is for testing a non-volatile memory. A base data pattern is defined for a first pageset of the non-volatile memory. The non-volatile memory has a plurality of pages which comprise words. The base pattern is arranged so that each bitpair of a plurality of bitpairs that includes one of a group consisting of even bitpairs and odd bitpairs formed from all of the words exhibits all possible bitpair transitions during sequential accesses of the pages of the plurality of pages. The base pattern is stored in the first pageset. The pages of the plurality of pages of the first pageset are accessed sequentially.

Abstract: A circuit comprises a switch, a driver circuit, and an open circuit detector. The switch has a first current electrode coupled to a power supply terminal, a second current electrode coupled to supply a current to a load, and a control electrode. The driver circuit has an input for receiving a control signal, and an output coupled to the control electrode of the switch. The open circuit detector has a first terminal coupled to receive a voltage from a bootstrap capacitor, a second terminal coupled to the power supply terminal, and a control terminal coupled to the driver circuit. The open circuit detector detects an open circuit, and in response, provides a signal at the control terminal for causing the driver circuit to open the switch.

Abstract: A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.

Abstract: A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition.

Abstract: A method for handling an interrupt during testing of at least one logic block of a processor includes performing a test on at least one logic block of a processor; during the performing, receiving an interrupt; determining a progress status of the test in response to receiving the interrupt; and determining when the processor responds to an interrupt, wherein the determining when the processor responds to an interrupt is based on the progress of the test.

Abstract: A method is provided for forming a semiconductor device having nanocrystals. The method includes: providing a substrate; forming a first insulating layer over a surface of the substrate; forming a first plurality of nanocrystals on the first insulating layer; forming a second insulating layer over the first plurality of nanocrystals; implanting a first material into the second insulating layer; and annealing the first material to form a second plurality of nanocrystals in the second insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.

Abstract: A method is provided for forming a semiconductor device having nanocrystals. The method includes: forming a first insulating layer over a surface of a substrate; forming a first plurality of nanocrystals on the first insulating layer; implanting a first material into the first insulating layer; and annealing the first material to form a second plurality of nanocrystals in the first insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.

Abstract: A snoop look-up operation is performed in a system having a cache and a first processor. The processor generates requests to the cache for data. A snoop queue is loaded with snoop requests. Fullness of the snoop queue is a measure of how many snoop requests are in the snoop queue. A snoop look-up operation is performed in the cache if the fullness of the snoop queue exceeds the threshold. The snoop look-up operation is based on a snoop request from the snoop queue corresponding to an entry in the snoop queue. If the fullness of the snoop queue does not exceed the threshold, waiting to perform a snoop look-up operation until an idle access request cycle from the processor to the cache occurs and performing the snoop look-up operation in the cache upon the idle access request cycle from the processor.

Abstract: A conductive via and a method of forming. The conductive via includes a portion located between a conductive contact structure and an overhang portion of a dielectric layer located above the conductive contact structure. In one embodiment, the overhang portion is formed by forming an undercutting layer over the conductive contact structure and then forming a dielectric layer over the conductive contact structure and the undercutting layer. An opening is formed in the dielectric layer and material of the undercutting layer is removed through the opening to create an overhang portion of the dielectric layer. Conductive material of the conductive via is then formed under the overhang portion and in the opening.

Abstract: A method of testing a contact structure including exposing a gold layer of at least one contact structure of a support structure to a solution including glacial acetic acid and nitric acid; and determining a porosity of the gold layer of at least one contact structure after the exposing.

Abstract: A method of testing a memory includes generating a plurality of addresses, such as a test address, accessing contents of each of the plurality of addresses and storing them in storage circuitry, performing a test on the plurality of addresses, accessing the memory test circuitry by sending an access address to snooping circuitry, determining if the access address matches at least one of the plurality of addresses and generating at least one hit indicator in response thereto, generating a snoop miss indicator, determining if the snoop miss indicator indicates a miss, if the snoop miss indicator indicates a miss, accessing the memory in response to the access address, and if the snoop miss indicator does not indicate a miss, either storing snooped data from a interconnect master to a selected portion of the storage circuitry or reading the snooped data from the selected portion of the storage circuitry to the interconnect master.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: In a data processing system, a method includes receiving samples of a send path input signal (Sin) and samples of a receive path input signal (Rin); in response to receiving each sample of the send path input signal, providing a double-talk indicator to indicate whether or not double-talk has been detected; using the double-talk indicator to determine a double-talk density within a predetermined number of samples of the send path input signal or the receive path input signal; and using the double-talk density to provide a heavy double-talk indicator which indicates whether or not heavy double-talk has been detected. In response to the heavy double-talk indicator indicating that heavy double-talk has been detected, a heavy double-talk mode may be entered.

Abstract: A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines.

Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

Abstract: A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.

Abstract: In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time.

Abstract: A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.

Abstract: An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.

Abstract: In one form a device having an integrated circuit is rendered useless by providing a piezo element coupled to a voltage terminal of the integrated circuit of the device. A render useless signal is generated by any of several ways. The piezo element, in response to the render useless signal, renders in any one of several ways the device to be rendered useless. The piezo element, when disturbed, generates a voltage which is provided to the voltage terminal of the integrated circuit, the voltage being sufficiently high to render useless at least a portion of the integrated circuit. In other forms the render useless signal renders MRAM circuitry within the device useless by moving a magnetic field across the MRAM circuitry to vary resistance of memory reference cells. In one form the magnetic field is moved by spring-loading or pivoting a magnet that is released by the piezo element.