Abstract: A microcontroller (100) has a CPU (102) and memory (104). Memory (104) contains a memory array (200). A large portion of the array (200) is used to contain functional data for the CPU (102), but the array (200) also contains one or a few rows of memory content parity information. Once the array (200) is written with lasting data and/or software, a parity controller (208) will generate initial parity values which correlate to the contents of the memory array (200). This parity information is stored within the parity portion of the array (200). After generating the initial parity data, the parity controller (208) occasionally, upon some parity checking event, generates current parity from the data stored within the array (200). This current parity is compared against the parity portion of the array (200) using the parity logic (210). If errors are detected, it is clear that the software/data that was intended to be static and non-changing has experienced a leakage error, soft error event, electrical short, etc.