Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity.

Abstract: A nut, including a body further including a threaded cylindrical hole, for receiving a threaded member, an axis of the threaded cylindrical hole being substantially parallel to a longitudinal axis of the body and a protrusion, grippable between a thumb and forefinger, extending from the body in a longitudinal direction, where the protrusion may be manipulated to position the body to engage the threaded member with the threaded cylindrical hole.

Abstract: A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.