Abstract: A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

Abstract: A numeric data processor having an execution unit adapted to efficiently execute the complete set of floating point operations recommended by the IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std. 754-1985, in full compliance therewith. The numeric data processor is also adapted to evaluate a large set of transcendental functions, including trigonometric, logarithmic and exponential, consistent with the IEEE Standard, without requiring a "software envelope." In the processor, special hybrid forms of Volder's CORDIC digital approximator and Meggitt's digital approximator are implemented in a manner so as to require minimal additions or modifications to the form of the execution unit which is otherwise required just to execute the standard floating point operations.

Abstract: Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded source/drain modifications in a double poly non-volatile memory process include the possibility of leaving the spacers used to modify the peripheral source/drain regions in place in the array portion of the device. Alternate methods include the possibility of removing the spacers in the array portion without the addition of critical mask steps and of keeping the spacers out of the array portion entirely.

Abstract: A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.

Abstract: First and second unused bits of a multi-bit mapped register are utilized to control a desired function. Each of the bits are capable of assuming first and second stable states. The control function is enabled when the first bit is in the first state and the second bit is in a second state. The function is disabled when the first bit is in the second state and the second bit is in the first state. The function remains unaltered when the first and second bits are each in the same state.

Abstract: A paged memory management unit (PMMU) adapted to prevent unauthorized access by a calling module executing in a data processor to a called module having a higher access level. A Stack Change Control Register in the PMMU has a bit corresponding to each valid access level. If the PMMU determines that any bit in the Stack Change Control Register corresponding to an access level between the access level of the calling module and the called module, including the access level of the called module, is set, a Change Stack bit in a Status Register is set to indicate that the processor should allocate a new stack for the called module. Both the Stack Change Control Register and the Status Register are accessible to the processor.

Abstract: A structure for implementing a plurality of independent filters, such as finite impulse response filters, in an efficient manner. Coefficient and data operands associated with each of the independent filters are stored in a predetermined order in a storage device and selectively coupled to an arithmetic unit for processing in a predetermined manner. Calculations for each filter are successively made and selectively stored. Although independent filters exist, processing circuitry is multiplexed and shared to substantially minimize associated control circuitry.

Abstract: The current microinstruction of a micromachine enables a selected one of a plurality of conditions to select one of a plurality of microaddress qualifiers to be combined with a specified base microaddress to form the next microaddress for the micromachine.

Abstract: A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

Abstract: In a random access memory a write driver develops a full rail write signal which is coupled to the selected bit line pair via transmission gates. The bit lines are thus driven to full rail. This results in a faster rise time on the bit line which is driven to a logic high. With the faster rise time, the selected cell is written into more quickly with the result of a faster write time for the memory.

Abstract: A process for forming lightly doped drains in a CMOS circuit utilizing two photoresist masks is disclosed. After gates for N-channel and P-channel transistors have been formed, an N-implant is effected. A first photoresist mask is used as a source/drain implant is made for the P-channel transistor. Sidewall spacers are formed for the gates of both transistors. A second photoresist mask is used as a source/drain implant is made for the N-channel transistor. The resulting CMOS circuit has an N-channel transistor with a lightly doped drain and a P-channel transistor without a lightly doped drain.

Abstract: A circuit for adding two N-bit binary numbers with an input carry bit, where N is an integer, by the carry select technique is provided. A ranked ordered plurality of section adders function in conjunction with rank ordered carry select logic circuits to initially provide two sum bits and two output carry bits for each bit position corresponding to carry input bits of zero and one, respectively. The section adders comprise full adders and are divided into at least two ranked groups in which sum bits are concurrently calculated in each group. Each full adder concurrently provides two sum bits for each rank ordered output sum bit. The rank ordered carry select logic circuits sequentially provide carry select bits which are used by the full adders to select one of the two sum bits as the output sum bit. Two output carry bits are concurrently provided by each group. One of the two output carry bits of the lowest ranked group is provided as a half carry output bit in response to the carry input bit.

Abstract: In a paged memory management unit (PMMU), a translation control (TC) register contains a set of table indexes which define the number of bits of the logical address to be used to access the translation table at the respective levels. The TC register also contains an initial shift field which defines the number of high order bits of the logical address to be discarded before an address translation, and a page size field which defines the number of low order bits of the logical address comprising the page address. Each descriptor in each translation table contains a descriptor type field which defines whether that particular descriptor is a translation descriptor or a pointer descriptor. If a pointer descriptor is encountered at a table level other than the lowest level, the translation table walk is terminated early and the translation performed using that pointer descriptor. In general, a table may occupy either the lower or upper portions of the page in which such table is stored.

Abstract: A write drive data control circuit for controlling the transmission of data to a memory array includes data input means for receiving complimentary data signals which are then transmitted to output circuits. The valid data is latched and the input circuits disabled. The output circuits remain enabled so as to pass the latched data to the memory array. After a predetermined period of time, the output circuits are disabled. In this manner, both the data set up time and data hold time may be independently optimized.

Abstract: A memory has a transmission gate requiring complementary signals for coupling a bit line to a data line. The complementary signals are generated utilizing a simplified circuit which does not require complementary predecoded signals. Two predecoded signals are further decoded by a circuit which provides the signals needed by the transmission gate. Although simplified circuitry is used, all of the voltage levels provided by the circuitry have a steady state at either the positive power supply or at ground so that there is no steady state current drain caused by signals that are not full rail.

Abstract: A paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of the logical address and a first table pointer to access a first one of the pointer tables to obtain therefrom a page table pointer to a selected one of the page tables and then combining a second portion of the logical address and the page table pointer to access the selected page table to obtain therefrom the physical address. If desired, an address space selector may be considered as an extension of the logical address.

Abstract: A data processor (2) including a watchdog timer (8) comprising: a first memory (4) holding a primary operating routine for cyclic execution during operation of the data processor, an address bus (6) for addressing locations in said first memory means, a timer (10) for continuous operation during operation of the data processor and for effecting a system reset in response to the timer reaching a predetermined value, the primary operating routine including at at least one predetermined location an instruction to reset the timer, whereby in normal operation of the data processor the timer does not reach the predetermined value, wherein the data processor further includes a second memory (12) for holding the address of the location containing the instruction to reset the timer, and a comparator (16) coupled to the address bus and the timer for preventing the timer from being reset in response to an instruction to reset the timer unless the address on the address bus is held in the second memory.

Abstract: A non-charge-sensing high density dynamic random access memory (DRAM) cell using a trench capacitor as a vertical FET and two active field effect transistors (FETs). A particular bit line is shared by the cells on either side of it; the bit line on one side of a particular cell being used to write to the cell while the bit line on the other side of the cell is used to read from the cell. This dual use of bit lines, plus the use of a vertical FET transistor along one side of a trench capacitor, plus the avoidance for the need of a relatively large storage capacitor since the cell is not read by "dumping" or releasing its charge onto the bit line all aid in making this cell compact and suitable for high density memories. Since the substrate serves as the second source/drain region of the vertical FET, a separate line for this region is eliminated, also contributing substantially to a smaller cell size.

Abstract: A microcomputer has the capacity for executing instructions, requesting prefetches of instructions, and experiencing a change in instruction flow, or a branch. The microcomputer also knows in advance that a change in instruction flow is going to occur. At such time that a branch becomes known there may also be a pending instruction prefetch request. Because a branch is going to occur, there is no need to execute the prefetch. Consequently, the pending instruction prefetch is flushed which thus avoids wasting time making an unnecessary instruction prefetch.

Abstract: A memory provides a byte program mode which avoids unnecessary erase and program cycles. If a byte is to be programmed, the new data to be written is first compared to the existing data in the byte. If the old data is the same as the new data, there is no need to do a conventional erase/program cycle. In such case the memory does not perform the erase and reprogram which saves much time and avoids decreasing the life of the floating gate transistors in the byte. Even if the old data is not the same as the new data, the byte may already be in the erased state. In such case the erase cycle is skipped and programming is begun.