Abstract: A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array.

Abstract: An arrangement and method for adjusting the brightness of an image signal having digital pixel values to produce brightness adjusted output pixel values is provided with an adder and lower and upper clamp circuits. The adder adds a brightness value to the digital pixel values of the image signal to produce adjusted pixel values and a carry-out signal. The lower clamp circuit clamps the adjusted pixel values to a lowest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values below the lowest output pixel value. The upper clamp circuit clamps the adjusted pixel values to a highest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values above the highest output pixel value.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: A method and apparatus for arbitration among users for a resource has a single shared user request line over which each of the users asserts request signals for use of the resource. Dynamic priority assignment is provided, in which the sequence of users is changed as a function of the last user to use the resource. A time multiplexed format for arbitration is followed, with each user keeping track of which user's turn it is to request use of the resource. This prevents starvation of an individual user and allows great flexibility in assigning priority to the users, while reducing pin counts and signal traces.