Abstract: An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into said encapsulant so that the electrical contacts make contact with said presoldered pads. Heat is applied to first activate said flux material and then reflow the solder on said presoldered pads to bond said SMD contacts to said presoldered pads. The reflow temperature is maintained for about 180 seconds during which time the resin solidifies. The resin encapsulant fills the space between substrate and SMD and forms fillets around the solder bonded contacts.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: An optical detection and measurement system for selectively detecting the plane of the reflective surfaces of a workpiece. A laser source provides a low power, single wavelength collimated beam of light which is directed onto a workpiece. The beam is passed through a converging lens to a reflected focus on a quad detector. The light beams reflected from the workpiece pass through a diverging lens to the quad detector. The non-diverging optical axis center of the diverging lens is aligned with the center of the quad detector so that a reflected beam passing through the non-diverging optical axis center of the diverging lens creates equal photocurrent outputs from each of the four photosensitive elements of the quad detector to produce a null condition. Where the workpiece is made up of translucent or transparent layers which produce multiple reflected beams, reflected beams from surfaces other than the surface of interest are deflected away from the active surface of the quad detector by the diverging lens.

Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract: A heat dissipating flexible or resilient standoff is mechanically clamped between an electronic module and substrate, such as, PCB. The clamping arrangement comprises a heat sink compressing a thermally conductive flexible interface pad over the upper surface of the electronic module by way of mechanical linkage to the PCB. The heat dissipating flexible standoff provides a force opposing the compression force to thereby reduce stress on solder ball connections between electronic module and PCB. Thermally conductive flexible standoffs in the form of spring arrangements, such as a wire mesh, act to provide heat dissipation by both thermal conduction and thermal convection. A thermally conductive flexible polymer pad and a layer of porous metal foam may also act as thermally conductive standoffs.

Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

Abstract: A heat sink structure is formed by stacking a plurality of heat sink layers. Each layer comprises an array of vertically disposed heat dissipating elements extending from a base plate. Cut outs are formed in each of the base plates to form openings so that when the layers are stacked, each of the ascending successive layers has a larger opening than the layer upon which it rests. Cooling may be by forced air or natural convection. With forced air, air impinges on the top of the stack and into the opening in the base plates. Because of diminishing size of the openings in the stack, a portion of the air is forced out the sides of each layer. With natural convection, air is drawn into the sides of each layer and the hot air at the center flows upwardly through the openings with increasing volume as it rises.

Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Abstract: A process for forming a bump via to interconnect upper and lower circuits wherein a layer of metal is etched down, leaving a bump via and a lower portion of the layer. A lower circuit pattern is then formed in the lower portion, following which the pattern and bump via are covered with an insulating layer. Smoothing then results in the top surface of the bump via being exposed such that an upper circuit can then be formed on the insulating layer and in connection with said bump via.

Abstract: An electronic package includes a substrate having a contact pad thereon, a reformable member such as a solder ball positioned on the contact pad, and an elastic member positioned around the reformable member. The elastic member exerts a girdling force on the reformable member so that when the reformable member is softened, the elastic member elongates the reformable member. This elongation accommodates thermal and other stresses between the foregoing substrate and another substrate joined at the free end of the reformable member. An apparatus is also provided for positioning the elastic member on and around the reformable member.

Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: A flip-chip module is interconnected to a PCB or circuit card through a peripheral LGA interposer connector. The flip-chip is mounted on the same surface of the module substrate as the peripheral array of LGA interconnection pads and projects into a central opening of the interposer. An opening in the upper stiffener of the PCB or circuit card permits the peripheral array of LGA interconnection pads to make contact with corresponding LGA PCB or circuit card pads. A first heat sink is arranged to thermally contact the entire surface of the substrate opposing the surface upon which the flip-chip is mounted. An opening in the PCB or circuit card and lower stiffener allows a second heat sink to make thermal contact with the surface of the flip-chip.

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

Abstract: The dielectric constant of low loss tangent glass-ceramic compositions, such as cordierite-based glass ceramics, is modified over a range by selective addition of high dielectric constant ceramics, such as titanates, tantalates and carbides and metals, such as copper. The low loss tangent is retained or improved over a range of frequencies, and the low CTE of the glass-ceramic is maintained. BaTiO3, SrTiO3 and Ta2O5 produce the most effective results.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A Land Grid Array electronic package having an array of contact pads is connected to a corresponding array of contact pads on a circuit board through a matching array of conductive pins of a flexible interposer. Alignment of the electronic package to the flexible interposer and flexible interposer to the circuit board is obtained by registration of alignment components to the contact pads and conductive pins. A pair of alignment components, such as pin-like alignment structures, on selected pads of both the electronic package and circuit board mate within alignment holes at the sites of corresponding pin locations in said flexible interposer. Alternatively, the pin-like alignment structures on the electronic package can be extended to pass through the said alignment holes of said flexible interposer into alignment holes which replace the pin-like alignment structure on said circuit board.

Abstract: A layout pattern for increasing the spacing between the deep trenches of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact to bitlines arranged in one direction and each of which cell pairs are coupled to gate conductors arranged orthogonal to the bitlines. The layout pattern is formed by positioning the deep trenches of all of said pairs along alternate bitlines so they are offset from said bitlines along gate conductors in opposing directions. The deep trenches of all of the remaining bitlines are offset from said bitlines in opposing directions opposite to the opposing directions of said trenches along said alternate bitlines so as to form a herringbone pattern of cells.