Abstract: The functions of two virtual operating systems (e.g., S/370 VM and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. The S/370 processors are alien to the S/88 Operating System, i.e., not in its configuration tables. Means are provided to isolate partner pairs of S/88 processors from the S/88 Operating System and couple the S/88 processors directly to corresponding pairs of S/370 processors for interaction therewith, transparent to the S/88 Operating System.

Abstract: A method of associating features, such as phone number directories, of a mobile communication module with individual NAMs in a communication module having a plurality of NAMs so as to provide accessibility to the directories based on the NAM activated for convenient and efficient access including the steps of establishing and comparing identification codes and further providing the option of changing phone number directories when changing NAMs or receiving the same NAM.

Abstract: This invention is directed toward a loop compensator which dynamically changes the compensation break points as a function of duty cycle, input voltage and output load current to insure system loop stability. The system identifier of the dynamic loop compensator identifies the converter circuit topology to which it is connected and relays corresponding circuit identification signals to a digital controller. Based on the identification signals, the digital controller implements one of three compensation algorithms that dynamically changes the compensation break points and consequently insures closed loop stability. Based upon system condition signals and one of the three compensation algorithms, the digital controller changes the compensation break points by producing variable frequency clock signals which are input into a bank of capacitors in a switching capcitor error amplifier network.

Abstract: An apparatus and method for providing variable bandwidth in wireless air-link communication channels which allows a user of an end-user communicating device, e.g. a cellular phone, computer, facsimile, to request the allocation and aggregation of available air-link communication channels for the wireless transmission of messages to and from a mobile end-user communication subscriber unit, e.g. a cellular telephone or portable computer, so as to increase the speed of wireless transmission, wherein information transfer networks, channelized communication radios and microprocessors are typically employed for locating, reserving and aggregating available air-link channels and for transmitting messages between end-user communication devices, one being mobile.

Abstract: A personal computer system is described, having security features enabling control over access to data retained in such a system. The system has a normally closed enclosure, at least one erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between entry and non-entry of any stored privileged access password.

Abstract: An apparatus is disclosed for quickly testing individual wiring nets in a multi-layer device carrier. A central processing unit (CPU) controls a probe to sequentially engage contact pads on the carrier, each of which is electrically connected to a respective wiring net. The probe connects each wiring net to a network sensitive pulse generator circuit which generates a train of output pulses having a frequency dependent upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates the series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response.

Abstract: The functions of two virtual operating systems (e. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques, The S/370 is limit checked prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A method and apparatus for rapid interconnection (hot plugging) peripheral device interface circuits to a computer bus is disclosed. The interconnections are completed using three sets of conductors in the sequence: common grounds, power from the bus and data lines. The time period between the interconnections is determined by the relative set back lengths of the conductors from the card edge and allows for stabilization of voltage and establishment of a stable high impedance state for the peripheral device controller circuits before the data lines are interconnected.

Abstract: In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

Abstract: Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining.

Abstract: A word addressable random access memory includes additional logic permitting accessing on bit boundaries during read/write operations requiring only one memory cycle. During each memory cycle, two "adjacent" word locations are selected for access concurrently in response to the decoding of one address. Logic responsive to bit boundary select signals determine which memory cells of the two "adjacent" word locations are in fact accessed to store or retrieve a word of data. In one preferred embodiment, the boundary select logic controls the data in/out lines of a pair of odd/even arrays. In another preferred embodiment, the boundary select logic includes logic within each cell of a single memory array.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contigous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A cache storage system is disclosed which has a high speed buffer (cache), a directory-look-aside-table, and apparatus for maintaining binary coded information signifying the order of use of various sections of the cache. A separately addressable and controllable storage array is provided for each bit position of the binary code so that updating of a code is accomplished by selectively writing certain but not all of the bits in the arrays storing said bits to be updated. This avoids the need to read all bits from an array, change the appropriate bits, then write all bits back into the array. Bits signifying the changed or unchanged state of data in said various sections of the cache are also stored in separately addressable arrays to permit updating of their value merely by selectively writing to the appropriate array.

Abstract: At least-recently used (LRU) storage means and its associated logic maintain usage history for associativity class entries of a cache directory. The storage means includes an independent storage array for each of the bit positions of an LRU binary code pattern. Parity bits are provided in the arrays for each LRU bit. Separate read/write controls simultaneously write updated LRU bits to some of the arrays and read out unchanged LRU bits from the remaining arrays during updating of a usage history entry when its associativity class is used. Pattern checking logic collects the update bits and the unchanged bits during the update cycle to determine whether or not the new entry is a valid LRU combination. A parity bit is written with each of the update LRU bits written into the arrays and parity bits are read out from the arrays with the unchanged LRU bits for parity checking of each unchanged LRU bit during updating of usage history entries.