Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and the reset signal. The second circuit may be configured to (i) switch a pull up signal in response to the pump up signal, (ii) switch a pull down signal in response to the pump down signal, and (iii) present the reset signal in response to switching the pull up signal and the pull down signal.

Abstract: A device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second signal interface. A second programmable logic device may be configured to have (i) a third signal interface and (ii) a fourth signal interface. The assembly apparatus is generally configured to (i) mount the first programmable logic device and (ii) mount the second programmable logic device. A first external contact may be connected to the first signal interface. A second external contact may be connected to the fourth signal interface. A direct connection may be provided between the second signal interface and the third signal interface.

Abstract: A test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester may be configured to (i) stimulate the first function with a test signal to present a first output signal, (ii) stimulate the final function with the first output signal to present a final output signal; (iii) measure a result between the test signal and the final output signal, and (iv) allocate the result between the first function and the final function to disperse a measurement error in the result.

Abstract: A circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.

Abstract: A circuit than may be used in an integrated circuit capacitor design. The circuit generally comprises a multilayer capacitor and a buffer. The multilayer capacitor may be configured as (i) a first capacitance, (ii) a second capacitance, and (iii) a third capacitance in series between the first capacitance and the second capacitance. The buffer may be configured to maintain a constant voltage across the third capacitance to isolate the first capacitance from the second capacitance.

Abstract: A circuit comprising a current source, a first amplifier, and a second amplifier. The circuit may be used to provide for crossing point compensation of a CMOS driver as a function of a supply voltage. The current source may be configured to present a reference current. The first amplifier may be configured to (i) receive the reference current as a load, (ii) receive a first voltage, and (iii) present a second voltage responsive to the first voltage. The second amplifier may be configured to (i) receive the second voltage and (ii) change a current at a node responsive to the second voltage.