Abstract: A method and apparatus are provided for detecting stale write data bugs associated with storage systems. The detection is accomplished by choosing a data pattern signature for each block of a storage device to be tested. The data pattern signature is then stored in a write log table which provides an index as to the data pattern signature associated with each block. Then, the block is filled by writing, in a repeating fashion, the data pattern signature until all bytes of the block have been written. At a later time, the entire block is read from the storage device. Once read, each byte retrieved is compared against the value of the data pattern signature currently stored in the write log for that block. If a mismatch is detected, then the error is reported and stored in a error log so that the bug may be eliminated.

Abstract: A digital data storage subsystem stores data for use by digital data utilization device. The data as used by the digital data utilization device being organized in the form of variable-length records. The digital data storage subsystem includes a digital data storage device, a cache and a cache control. The digital data storage device has at least one fixed block storage unit for storing a predetermined amount of data, the storage unit storing at least one record and additional padding if the record does not comprise at least said predetermined amount of data. The cache including at least one cache slot which can accommodate the storage of the predetermined amount of data, that is, the amount which can be stored on the block storage unit of the digital data storage device.

Abstract: A reduce cross-talk wiring harness and method for accomplishing same. The wiring harness is used for routing signals from a bus and tag housing to a controller, and for routing signals back from the controller to terminators in the bus and tag housing. The harness includes an input pair and an output pair of bus and tag ribbon cables. The cables in each pair are of essentially the same length. Each pair has a combined bus and tag connector attached to one end, and individual bus and tag connectors attached to the other end. The input and output bus and tag ribbon cables are grouped together for at least part of the distance between the controller and the bus and tag housing in such a manner that at least one of both bus cables or both tag cables are adjacent one another, to reduce cross-talk between the bus cable of one cable pair and the tag cable of the other cable pair.

Abstract: Two data communication channels having electrical ground positions that alternate with control and data positions are terminated in a single, dual-channel connector that occupies generally the same interconnection board real estate as is required for a single, prior art, data communication SI connector, such as for a Small Computer System Interface (SCSI) communication channels. A two-channel SCSI connector system and connection method includes providing a two-channel header having two ground buses, to which the alternating electrical ground wires of respective first and second SCSI channels are terminated. Only a few of the pins or positions of the two-channel connector are connected to the two ground buses while the majority of pins or positions are connected to the signal (control, data) wires of the two SCSI channels.

Abstract: A shared system memory buffers data transfers between a plurality of host computers and a plurality of data storage devices. The system memory includes a cache memory and a number of queues and structures to facilitate performance. Management of a replacement queue within the system memory is based on the elapsed time and usage of the data element. If the elapsed time of a data element to be updated is less than a threshold, the data element will remain in the same location of the replacement queue; if the elapsed time is greater than the threshold, the data element is placed at the tail of the replacement queue. The threshold may be determined by dynamically monitoring the stress of the cache memory. The updating of the replacement queue is also affected by the number of times the data element has been accessed while in the replacement queue. The memory also includes a pending write data structure which is not part of the replacement queue.

Abstract: A method of prefetching data from the storage media of a data storage system, in which the data is stored on, and read from, the storage media in individually-accessible data storage portions, such as tracks of a hard disk. A number of immediately past-read data storage portions are used to predict a storage portion or portions that will likely be requested in the future. The unique identifiers of those previously-read data storage portions are determined, and a prediction coefficient is calculated for each unique identifier. The prediction coefficient is then multiplied by the unique identifier, and the results are summed to determine the unique identifier of a data portion to be prefetched.

Abstract: A cache management system and method monitors and controls the contents of cache memory. A time indication provider provides a time indication signal to a cache indexer, for maintaining a cache index which are stored in cache as well as an indication that a data element must be written to a longer term data storage device. A cache manager is responsible for placing data elements into and removing data elements from the cache memory. The cache manager is responsive to at least one data element stored in cache which must be written to a longer term data storage device, and to the associated time indication, for determining the amount of time that the data element has been stored in cache as well as the average period of time that elapses between a data element being inserted in cache and being removed from cache.

Abstract: A method and apparatus are for maintaining a cyclic redundancy check (CRC) byte is described which eliminates additional input/output (I/O) transactions for the case when a write to a partial sector is required while the CRC byte is maintained for an entire sector. The method includes performing an XOR operation between the partial write data and the data it is to displace, and then performing an XOR operation between the old CRC byte associated with the sector and the result of the XOR operation between the partial write data and the data it is to displace.

Abstract: A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.

Abstract: First and second pairs of pins and cooperative first and second pairs of pin receiving apertures are provided at the confronting connector faces of each of one or more data storage device carrier subassemblies and an interconnection board of a storage system card cage subassembly into which each data storage device carrier subassembly is slidably mounted. The first pin/aperture pair engage and cooperate first to prealign, mechanically support and vibrationally damp each data storage device carrier subassembly.