Abstract: A system for programming a computer provides a set of software-based virtual machines each for instructing a computer to carry out a selected operation. Each virtual machine is represented by a virtual front panel displayed on a screen and each virtual front panel graphically displays operator controllable values of input and output parameters utilized by the virtual machine it represents. The system is adapted to synthesize a new virtual machine for instructing the computer to perform a sequence of operations wherein each operation is carried out by the computer according to the instructions of an operator selected one of the existing virtual machines. The system also creates a new virtual front panel for displaying input and output parameters associated with the new virtual machine. The system permits the operator to program the computer by directing synthesis of a hierarchy of virtual machines.

Abstract: A min/max time stamp for a multimeter provides display of minimum and maximum measured values recorded since enabling a min/max function. The minimum and maximum values, as well as a present value, may be displayed, together with the relative or absolute time at which the measured minimum or maximum occurred. An alert signal is generated to indicate a new maximum or a new minimum measurement.

Abstract: An improved open circuit detector for testing a thermocouple for an open circuit condition. The detector includes a generator for providing and sourcing a tone signal to the thermocouple, wherein the tone signal has a known frequency and amplitude. A monitor analyzes the amplitude of a particular frequency component of a tone signal across the thermocouple. If the amplitude of the particular frequency component exceeds a predetermined threshold, an output is provided for indicating an open circuit condition for the thermocouple.

Abstract: A coupling circuit for a multimeter adapted to perform multiple measurements includes a thermistor and constant current sources in series between an instrument input terminal and an instrument circuit adapted to source current for ohms measurements. Varistors shunt the constant current sources and are thermally coupled to the thermistor. An initial inrush of current is controlled by the constant current sources and when the voltage across a constant current source reaches the knee voltage of the paralleled varistor, the varistor shunts the constant current source and provides heat to the thermistor for insuring the latter will transition to its high resistance state. The thermistor then drops a substantial part of the input voltage, effectively disconnecting the low impedance ohms circuit from the input terminals and protecting the constant current source circuitry and varistors from extended application of high voltage.

Abstract: An improved circuit simulator interface permits a user to define one or more output parameters describing behavior of hierarchically-defined subcircuits of a circuit. The user defines each output parameter by a hierarchial expression including one or more primitive output parameters generated by a simulator when simulating the circuit or other user-defined output parameters describing behavior of subcircuits of the circuit. Once the circuit simulator has simulated the circuit and has generated the primitive output parameter values, the simulator interface responds to a user request to display the value of a selected user-defined output parameter by decomposing the hierarchical parameter expression defining the selected output parameter to an expression combining only primitive parameter values. The simulator interface then evaluates the decomposed expression using primitive parameter values generated by the simulator and displays the result.

Abstract: An analog-to-digital converter latching circuit functions alternatively in a degenerative mode and a regenerative mode. During degeneration, circuit stray capacitances are substantially discharged for resulting in fast operation. When the circuit switches from degeneration to regeneration, a small signal current is able to start the latch in the proper direction without first having to overcome charge stored in the stray capacitances.

Abstract: An electronic instrument is provided with a shielding system consisting of two metallic shields press fitted into plastic instrument case parts without the need for any additional parts to provide electrical and mechanical attachment. In one embodiment, a bottom shield is press fitted onto protuberances inside of a lower case part and electrically connected to a common jack base on a circuit board within the instrument by a vee spring on the bottom shield. A top shield is press fitted into a capturing region of a switch support case part and includes an extension arm and extension ring that is mechanically held by case screws and guides already required by the plastic case. In that position, the extension ring is held in electrical contact with a common pad on the circuit board, the common pad being in electrical contact with a common trace, a common area, and the common jack base.

Abstract: A low impedance overvoltage protection circuit includes a first MOSFET having a drain connected to an input signal and a source connected to a drain of a second MOSFET, the source of the second MOSFET being coupled to the output. The gates of the first and second MOSFETs are connected to voltage supplies which float relative to the input signal values so as to maintain the gates of the respective MOSFETs biased to a conducting state. The maximum and minimum values to which the floating voltage supplies will float are defined by clamping diodes and clamp voltage sources. When the input signal value exceeds a desired positive maximum value, the first MOSFET is no longer biased to an on state whereby the MOSFET turns off, shunting the input signal through a high impedance for limiting input current and removing the input signal from the output. Negative going peak values are removed in a like manner by the second MOSFET.

Abstract: An analog-to-digital converter comparator circuit includes a pair of differential amplifiers having their outputs normally intercoupled in a subtractive sense. At a sampling strobe time, the output of one differential amplifier is reversed such that outputs of the two differential amplifiers are additive. The period of time during which the output signals add can be made as short as desired, for example by successively operating differential coupling circuits at the amplifier outputs through an intervening delay line. A very small aperture time is secured which is substantially shorter than the time constant of subsequent circuitry. A latch circuit receives the output of the comparator for assuming one of two different states in accordance with the comparator sampled output.

Abstract: The capacitance of an unknown capacitor is measured with multimeter instrumentation employing a dual slope analog-to-digital converter. The initial voltage across the capacitor is measured and the capacitor is cyclically charged until the capacitor reaches a predetermined proportion of possible charge. The final voltage is measured. The voltage across the charging resistance is integrated over successive charging cycles to provide a value proportional to the charge delivered to the capacitor and this value is divided by the difference between the initial and final voltages.

Abstract: A pair of waveforms in quadrature relation, or otherwise phase related, are generated from a single direct digital synthesizer employing a single wave lookup table memory. Successive addresses are applied to the memory representing the desired phase difference between the two waveforms plus a fractional part of the increment desired between successive samples along the waveforms. Samples are selected for reconstructing the two respective waveforms by dividing down the sampling clock and providing timing signals therefrom coincident with the correct samples.

Abstract: A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

Abstract: A bus-to-bus interface circuit maps a portion of the address space of each bus to a corresponding portion of the address space of the other bus. When a computer processor one one bus attempts to read or write access a mapped address, the bus interface circuit obtains control of the other bus and read or write accesses a corresponding address on the other bus. The interface circuit permits a bus master on the first bus to lock both buses so that it may perform several bus-to-bus data read or write operations without having to re-arbitrate for control of either bus after each operation.

Abstract: A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lines and synchronized by a common clock signal. The transmission lines interconnecting the integrated circuits are formed by thin metallic foil conductors separated by dielectric polyimide membranes. The clock signal is adjustably delayed prior to transmission to each integrated circuit so that pulses of the clock signal arrive at each integrated circuit at the same time regardless of differences in inherent delays of the separate paths the clock signal must follow to each integrated circuit.

Abstract: A sampling streak oscilloscope responsive to a light input signal stores charges on a CCD target by means of an electron beam rapidly scanned across a narrow dimension of the CCD target in coincidence with a segment or portion of the light input signal. The time relationship between a streak and the light input signal is changed to record a charge pattern for another segment of the input signal, while charges representative of a prior segment are transferred along the CCD array. A representation of the entire input signal is built up in memory.

Abstract: A system for testing electronic devices includes a waveform generator, a data acquisition system, and a computer. The waveform generator continuously generates a test signal having adjustable parameters set by the computer in response to user input. The data acquisition system acquires data representing the output of the device under test in response to the input signal and stores the last N acquired data values. The computer transfers a data sequence from the acquisition system to another memory and generates in a window on a terminal screen a wagveform display representing the stored data sequence. The computer also displays menu items referencing mathematical operations that may be performed on one or more data sequences. When a user selects one of the menu items, the computer prompts the user to select one or more windows containing waveform displays. Thereafter, the computer performs the selected operation on the data sequence controlling the waveform displays in the selected windows.

Abstract: An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus.

Abstract: The charge transfer efficiency of a two-phase charge-coupled device cell is enhanced by providing a three-tiered built-in potential in the channel of each cell. Two lower potential tiers form a trenched potential well in the cell for storing charge. A higher potential tier between the trenched potential well of a cell and the potential well of a preceding neighbor cell provides a potential barrier preventing backflow of charge from well-to-well. The potential trench is located at the downstream end of the well adjacent a succeeding neighbor cell of the CCD.

Abstract: An interface circuit board connected to a VMEbus standard backplane bus of a first data processing system, and also to a Futurebus standard backplane bus of a second data processing system, provides address/data conversion and interrupt service between the two standard bus structures. The Futurebus, being a higher level bus than the VMEbus, has no provision for hardware interrupts; event related data are conventionally transmitted across the Futurebus like any other data item. The interface board signals VMEbus interrupts to Futurebus devices by way of the Futurebus bus arbitration facility. Interrupts generated on the interface circuit board and interrupts from the VMEbus priority interrupt bus are mapped and converted into message numbers, one of which is asserted on the Futurebus arbitration bus as an arbitration number higher than the arbitration numbers assigned to Futurebus devices.

Abstract: A low distortion optic fiber network having a feedback system which injects pilot tones into a base band input signal directly modulating an LED, optically detects the output resulting from the pilot tones, digitally samples the detected signal, and generates correction coefficients. The correction coefficients and the base band input signal are input to a correction circuit that pre-distorts the input signal in a non-linear manner and uses the distorted signal to modulate the LED. Pre-distorting the LED input signal compensates for the non-linearities of diode transfer characteristics and intermodulation between signals in the network thereby reducing harmonic and intermodulation distortion.