Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.

Abstract: The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Abstract: An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the same cache way that the previous cache access was taken from. If the next cache access is taken from the same cache way as the previous cache access, the control circuit signals all the cache ways, except the cache way that was previously accessed, to not access information from their arrays. The control circuit also signals the tag arrays to not access their information and disables power to all the compare circuits. In this manner, power may be reduced when sequentially accessing information from one cache way in a multi-way set associative array.

Abstract: An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.

Abstract: In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled latch, a first wordline, and a first bitline. A first read-only transfer device is connected to a second bitline, a second wordline, and a first pull-down device. A second read-only transfer device is connected to the first bitline, the first wordline, and a second pull-down device. A clear memory transfer device is connected to the cross-coupled latch, a third bitline, and a third pull-down device. This configuration allows a reduction in the size of a dual-port SRAM cell with little or no reduction in the read access time of the cell. The reduction in size also reduces SER by reducing the cross-sectional, p/n junction area exposed to radiation.

Abstract: An embodiment of the invention provides a circuit and method for improving noise tolerance in multi-threaded memory circuits. A PFET is added to the receiving input of each memory cell. The gate of the PFET is connected to the output of the memory cell and the source of the PFET is connected to the control signal of the memory cell. In the case where the dataline is charged near ground and a memory cell, with a high value, is read, and the control signal is high, noise tolerance is improved by the addition of the PFET to the memory cell. The invention does not introduce additional drive fights during writes, when the control signal is low.

Abstract: An embodiment of the invention provides a circuit and method for optimizing an index hashing function in a cache memory on a microprocessor. A programmable index hashing function is designed that allows the index hashing function to be programmed after the microprocessor has been fabricated. The index hashing function may be “tuned” by running an application on the microprocessor and observing the performance of the cache memory based on the type of index hashing function used. The index hashing function may be programmed by several methods.

Abstract: In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.

Abstract: An embodiment of this invention provides a system and method for sensing the status of a ZIF socket lever. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a electrical contact on the socket. When the ZIF socket lever is closed, the other lead of the LED is connected to a ground. As a result, the LED is activated indicating the ZIF socket lever is closed.

Abstract: An embodiment of this invention provides a system and method for indicating the orientation of a packaged IC in a socket. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a socket hole on the socket. When the orientation of the IC package in the socket is correct, the other lead of the LED is connected to a ground path on the packaged IC. As a result, the LED is activated indicating the orientation of the packaged IC is correct.

Abstract: A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to Nwells containing PFETs used in memory cells. When a memory cell is in standby, the voltage applied to Nwells containing PFETs is increased in order to reduce leakage current. When a memory cell is being written, read, or refreshed, the voltage applied to Nwells containing PFETs is reduced in order to allow the memory cell to switch more quickly.

Abstract: An embodiment of the invention provides a circuit and method for reducing power in dynamic circuits. A large single pre-charge FET is used to pre-charge the pre-charge nodes of all dynamic logic blocks contained in a plurality of dynamic logic blocks. The large single pre-charge FET replaces all smaller individual FETs that normally would be used. Because smaller FETs typically have more subthreshhold leakage than larger FETs, the overall subthreshhold leakage is reduced. The large pre-charge FET only replaces smaller pre-charge FETs that have the same pre-charge signal going to their gates.

Abstract: An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage transition is presented at one input of a two-input NOR gate and at the input of a circuit with three inverters in series. The output from the circuit with three inverters in series connects to the second input of the two-input NOR gate. This combination creates a voltage pulse that drives a transfer FET. The transfer FET creates a voltage on a latch. The latch stores the voltage presented on the input and then drives a delay-chain with an odd number of inverters. The output of the delay-chain drives a second transfer FET that resets the latch.

Abstract: A content addressable memory, CAM, cell wherein the only compare-transfer FETS used are NFETs. The gates of the NFET compare-transfer FETS are driven to a voltage above the positive power supply, VDD. By precharging the bitlines to the negative power supply voltage, GND, the gate of one of the compare-transfer NFETS is driven above VDD when a bitline transitions from a “low” value to a “high” value. The capacitance between the bitline being driven high and the gate of a compare-transfer NFET couples the gate higher than VDD. This bootstrapping technique improves the compare access time of a CAM. In addition, this technique reduces the capacitance on the bitlines resulting in faster read and write access times and reduces the physical size of the CAM.