Patents Represented by Attorney John R. Ley, LLC
  • Patent number: 7053639
    Abstract: A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted position for testing and optical failure analysis. The probe fixture includes a position adjustment mechanism to locate the entire probe above the wafer and to more precisely position a tip of the probe on the IC. Optical failure analysis techniques are performed on the front side or the back side of the wafer while the wafer is retained in the test fixture and the probes are connected to the IC.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: May 30, 2006
    Assignee: LSI Logic Corporation
    Inventor: Margaret S. Fyfield
  • Patent number: 6927079
    Abstract: A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted position for testing and optical failure analysis. The probe fixture includes a position adjustment mechanism to locate the entire probe above the wafer and to more precisely position a tip of the probe on the IC. Optical failure analysis techniques are performed on the front side or the back side of the wafer while the wafer is retained in the test fixture and the probes are connected to the IC.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: August 9, 2005
    Assignee: LSI Logic Corporation
    Inventor: Margaret S. Fyfield
  • Patent number: 6901207
    Abstract: An audio/visual (A/V) device, such as a DVD player, assists a user in finding desired programming from among DVD programs, conventional broadcast television (TV) programs and World Wide Web transmitted programs. The programs contain close caption (CC) and A/V content. The A/V device captures and stores the CC and/or A/V content either for current or later manual use by the user or concurrent automatic searching for desired program content or information. Text-based searching is performed on the CC content for a match with user-specified textual search criteria. The audio context is searched for either a change that indicates a change in programming or a match with user-specified audio search criteria. A video still image is captured from the video content for manual viewing or automatic comparison to a desired image. The A/V device also presents the information, including the A/V content, captured CC content and search results, on either a conventional TV or higher resolution progressive monitor.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: May 31, 2005
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins
  • Patent number: 6891219
    Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 10, 2005
    Assignee: LSI Logic Corporation
    Inventors: Derryl Allman, John Gregory
  • Patent number: 6846569
    Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: January 25, 2005
    Assignee: LSI Logic Corporation
    Inventors: John Hu, Ana Ley, Philippe Schoenborn
  • Patent number: 6825546
    Abstract: A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 30, 2004
    Assignee: LSI Logic Corporation
    Inventors: John Q. Walker, Todd A. Randazzo
  • Patent number: 6775453
    Abstract: A graded index of refraction optical waveguide is formed in interlayer dielectric material located above a substrate an integrated circuit-like structure. The waveguide includes a refractive layer of optically transmissive material surrounding a core of optically transmissive material within a trench in the dielectric material. The material of the core has a higher index of refraction than the refractive layer and the material of the refractive layer has a higher index of refraction than the dielectric material. More than one refractive layer may also be formed in the trench, with the inner refractive layer having an index of refraction higher than the outer refractive layer and less than the core.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Verne C. Hornbeck, Derryl D. J. Allman
  • Patent number: 6770947
    Abstract: A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Gary K. Giust, Ruggero Castagnetti, Yauh-Ching Liu, Shiva Ramesh
  • Patent number: 6760803
    Abstract: A bus interface and a receiver in the bus interface receive signals from a computer bus, such as a SCSI (Small Computer System Interface) bus, and deskew and synchronize the signals into valid data and control signals. The signals are aligned and then a portion of the signals is offset to ensure that the other signals have sufficient time to stabilize before being latched. The alignment is performed by adding and subtracting delay units to and from the signals. The offset is determined by a self-calibration logic that uses the same type of delay units.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Jeffrey J. Gauvin, Wiliam K. Petty
  • Patent number: 6743725
    Abstract: The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: June 1, 2004
    Assignee: LSI Logic Corporation
    Inventors: Rongxiang Hu, Philippe Schoenborn, Masaichi Eda
  • Patent number: 6728477
    Abstract: A DVD player or computer with a DVD drive simultaneously presents multiple angles of video on a display. DVD standards provide for formatting and storing video that was filmed from more than one angle. Desired angles are selected, and the DVD player multiplexes between each angle of the playback to decode video frames for each selected angle. The frames for each angle being played back are filtered down to a size that fits into a fragment of the display. Each of the filtered frames are assembled into a single frame that can be presented on the display to simultaneously playback each angle.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins
  • Patent number: 6725294
    Abstract: In a computer (e.g. an 80×86-compatible personal computer) in which peripheral devices (e.g. hard drives, floppy drives, CD-ROMs, etc.) are accessed through more than one chain of handlers for the peripheral devices (e.g. via interrupts 13h and 40h), an improved device handler for a peripheral device (e.g. a device that complies with the “El Torito” standard) is inserted in both chains (e.g. by “hooking” both interrupts 13h and 40h), so the device handler cannot be bypassed when an access request directed to the device handler is passed through either chain and so the device handler can direct the access request to the next device handler in the correct chain, when appropriate.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Derick G. Moore, Roy W. Wade
  • Patent number: 6678809
    Abstract: Block-level storage is managed in a computerized storage system by recording into a write-ahead log a description of block-level updates made to data in a volume in a main memory and in a storage device of the computerized storage system. The write-ahead logging enables directory updates for each block-level write request to be logged, so the write request can be allowed to complete independently of other write requests.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: January 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: William P. Delaney, Donald R. Humlicek
  • Patent number: 6672320
    Abstract: A drum washer has a base, a barrel support structure, and a water delivery system. A hollow drum is turned over and placed on the drum washer by inserting a spray head of the water delivery system through a hole in a top cover of the drum and into the interior of the drum. The barrel support structure holds the drum at a fixed angle while water is sprayed from the spray head onto interior surfaces of the drum. The water rinses the interior surfaces of the drum and drains out the hole in the top cover of the drum.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: January 6, 2004
    Assignee: LSI Logic Corporation
    Inventor: Don Rudolfs
  • Patent number: 6671846
    Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. A different logic cone is derived for each of the multiple failing output signals at output pads.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: December 30, 2003
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6656805
    Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: December 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Rajiv Patel, Ravindra M. Kapre
  • Patent number: 6653726
    Abstract: The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in the power distribution grid are generally L-shaped. Thus, the electrical conductors are arranged generally in symmetrical quadrants within which the electrical conductors extend from one side edge of the IC chip to a generally right-angled corner and then to a second side edge that is adjacent to the first side edge.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: November 25, 2003
    Assignee: LSI Logic Corporation
    Inventors: Richard T. Schultz, Roger D. Weir
  • Patent number: 6629203
    Abstract: An improved shadow directory technique allocates storage space for directories in pairs in a logical volume. One of the spaces in each pair is used for a directory for locating data in the logical volume. The other space is reserved for an updated copy (shadow) of the directory if the directory is ever to be changed or updated. After the shadow directory is stored, it becomes a new directory for locating the data in place of the previous directory. The storage space containing the previous directory is unused, but retained as allocated for the next shadow directory, if needed. Since directory storage spaces are not deallocated, the improved shadow directory technique enables a simplified sequential-allocation storage management in a primarily data-add environment.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventor: Donald R. Humlicek
  • Patent number: 6605951
    Abstract: Interconnectors are placed on a die containing a semiconductor device or integrated circuit which is to be tested or analyzed. The interconnector includes a bump contact for contacting a bond pad of the die, and a probe pad at a position spaced from the bump contact. An interconnector connects the bump contact and the probe pad. The interconnector is attached to the die with the bump contact in electrical contact with the bond pad and with the probe pad extending beyond an exterior peripheral edge of the die. Probes apply signals or power to the probe pad, and those signals and power are applied to the semiconductor device or integrated circuit to establish functionality for the test or analysis.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: August 12, 2003
    Assignee: LSI Logic Corporation
    Inventor: Joseph W. Cowan
  • Patent number: 6594744
    Abstract: In a storage system, such as a storage area network, a snapshot volume or one or more checkpoint volumes are formed from the same base volume using a single repository containing multiple images of data stored in the base volume. The first image is started with the formation of the snapshot volume or the first checkpoint volume and is filled with blocks of data copied from the base volume, thereby increasing in size within the repository, until the first image is stopped and the next image is started. The next image is then filled with blocks of data copied from the base volume until stopped. Thus, the blocks of data are copied only into the most recently created image within the repository. With the creation of each checkpoint volume, a new image is concurrently started in the same repository. Each checkpoint volume is dependent on the image that was created concurrently plus any images created thereafter.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: July 15, 2003
    Assignee: LSI Logic Corporation
    Inventors: Donald R. Humlicek, Rodney A. DeKoning, William P. Delaney