Patents Represented by Attorney, Agent or Law Firm John V. Silverio
  • Patent number: 6772388
    Abstract: An adaptive and dynamic forward error correction scheme for a communication channel is disclosed. The method and apparatus calculates the actual bit error rate for comparison with a target bit error rate. When a channel is performing better than required by the performance specifications, the forward error correction power can be reduced to provide greater throughput. If the calculated actual bit error rate is greater than the target bit error rate, then the forward error correction power is increased in an attempt to lower the calculated bit error rate. A feedback loop is employed to continually calculate revised bit error rates as the forward error correction power is increased or decreased.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: August 3, 2004
    Assignee: Motorola, Inc
    Inventors: Michael J. Cooper, Stephen Schroeder
  • Patent number: 6694149
    Abstract: A method and apparatus for reducing power consumption in a network device (104, 105, 106, 107) is provided. A network device (104, 105, 106, 107) is placed in a quiescent mode and scheduled to switch to an active mode at a scheduled time. At the scheduled time, the network device (104, 105, 106, 107) is activated. A control message (402, 403, 404, 405) is received by the network device (104, 105, 106, 107). The control message (402, 403, 404, 405) includes an indication as to whether or not the network device (104, 105, 106, 107) should remain in the active mode in preparation of receiving a data message (608, 609). If the control message (402, 403, 404, 405) indicates that the network device (104, 105, 106, 107) need not remain in the active mode, the network device (104, 105, 106, 107) sets a new scheduled time and returns to the quiescent mode.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: February 17, 2004
    Assignee: Motorola, Inc.
    Inventors: Roger W. Ady, Peter A. Kindinger, Robert G. Uskali
  • Patent number: 6269175
    Abstract: A method and apparatus for accurately computing parallax information as captured by imagery of a scene. The method computes the parallax information of each point in an image by computing the parallax within windows that are offset with respect to the point for which the parallax is being computed. Additionally, parallax computations are performed over multiple frames of imagery to ensure accuracy of the parallax computation and to facilitate correction of occluded imagery.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: July 31, 2001
    Assignee: Sarnoff Corporation
    Inventors: Keith James Hanna, Rakesh Kumar, James Russell Bergen, Harpreet Singh Sawhney, Jeffrey Lubin
  • Patent number: 6256423
    Abstract: An image is divided into one or more (e.g., foreground) regions of interest with transition regions defined between each region of interest and the relatively least-important (e.g., background) region. Each region is encoded using a single selected quantization level, where quantizer values can differ between different regions. In general, in order to optimize video quality while still meeting target bit allocations, the quantizer assigned to a region of interest is preferably lower than the quantizer assigned to the corresponding transition region, which is itself preferably lower than the quantizer assigned to the background region. The present invention can be implemented iteratively to adjust the quantizer values as needed to meet the frame's specified bit target. The present invention can also be implemented using a non-iterative scheme that can be more easily implemented in real time.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: July 3, 2001
    Assignees: Sarnoff Corporation, LG Electronics, Inc.
    Inventors: Ravi Krishnamurthy, Sriram Sethuraman
  • Patent number: 6243497
    Abstract: A method and apparatus for selecting a quantizer scale for each frame to optimize the coding rate is disclosed. A quantizer scale is selected for each frame such that the target bit rate for the frame is achieved while maintaining a uniform visual quality over an entire sequence of frames.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: June 5, 2001
    Assignee: Sarnoff Corporation
    Inventors: Tihao Chiang, Ya-Qin Zhang
  • Patent number: 6233256
    Abstract: A method and apparatus for analyzing and monitoring packet streams in “real time”. The packet analyzer comprises an input buffer, a real-time analysis unit, a non-real-time analysis unit, a graphics unit, a monitor and a flushing circuit. A packet stream is received into the input buffer where the data is either read by the real-time analysis unit or flushed by the flushing circuit. Messages are passed between the real-time analysis unit and the non-real-time analysis unit to report on detected errors or to update packet stream information. In turn, real time packet stream information are displayed and updated on a display via the graphic unit. A method of detecting framing errors in a packet stream is incorporated by setting a 9th bit in the input buffer for each byte of data in a packet.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: May 15, 2001
    Assignee: Sarnoff Corporation
    Inventors: Charles Benjamin Dieterich, Arthur Lee Greenberg
  • Patent number: 6219462
    Abstract: A method for performing parametric image alignment, which when given any local match-measure, applies global estimation directly to the local match-measure data, without first going through an intermediate step of local flow estimation. The method can utilize any local match-measure, such as, correlation, normalized-correlation, squared or absolute brightness differences, statistical measures such as mutual information, and the like.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: April 17, 2001
    Assignee: Sarnoff Corporation
    Inventors: Padmanabhan Anandan, Michal Irani
  • Patent number: 6208692
    Abstract: An apparatus and a concomitant method for performing hierarchial block-based motion estimation with a high degree of scalability is disclosed. The present invention decomposes each of the image frames within an image sequence into an M-ary pyramid. Different dynamic ranges for representing the pixel values are used for different levels of the M-ary pyramid, thereby generating a plurality of different “P-bit” levels, i.e., a plurality of different M-ary pyramid architectures. The present scalable hierarchical motion estimation provides the flexibility of switching from one M-ary pyramid architecture to another M-ary pyramid architecture according to the available platform resources and/or user's choice.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: March 27, 2001
    Assignee: Sarnoff Corporation
    Inventors: Xudong Song, Tihao Chiang, Ya-Qin Zhang, Ravi Krishnamurthy
  • Patent number: 5731743
    Abstract: A frequency synthesizer including a fixed frequency oscillator providing a plurality of waveforms having a first frequency, each waveform being delayed in time with respect to another of the waveforms, and a waveform selector, the waveform selector operable to continuously select as an output waveform a waveform from the plurality of waveforms. In an embodiment, the selection of the waveform is made to provide an output waveform having low jitter with respect to an ideal waveform.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: March 24, 1998
    Assignee: David Sarnoff Research Center, Inc.
    Inventor: Donald Jon Sauer
  • Patent number: 5583569
    Abstract: A video camera is adapted to provide an asynchronous computer-friendly output signal instead of a standard analog video format. The output signal becomes a digitally-encoded message wherein each video frame becomes a serialized string of digital data demarcated by a digitally-encoded initiator identifying the ensuing data as characterizing that entire frame. The beginning of the entire set of frames that comprise the total video message is identified by a special header comprising a time stamp code and a format code.
    Type: Grant
    Filed: August 19, 1994
    Date of Patent: December 10, 1996
    Assignee: Intel Corporation
    Inventor: Andrew Kuzma
  • Patent number: 5559831
    Abstract: A variable-length decoder system decodes a variable-length code having different code prefixes in an input bit stream. A code prefix is located in the bit stream and used to determine a number of bits to be selected from the input bit stream according to an access of a code book. Additionally, a pointer, directing access to a different code book, may also be indicated by the access of the first code book according to the located code prefix. A determination is made in this decoder system whether to perform the operation of determining a number of bits to be selected from the input stream or accessing a second code prefix table. If the code value is valid, the number of bits is selected and appended to the code prefix to form a code word which is later decoded by the system of the present invention. If another table is indicated a further code prefix is located in the input stream and the further lookup table is accessed in accordance with the further code prefix.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: September 24, 1996
    Assignee: Intel Corporation
    Inventor: Michael Keith
  • Patent number: 5542451
    Abstract: A water distributor for distributing a flow of water to at least one of a plurality of output ports. The particular output port(s) chosen varies as a function of time and depends on the position of a motor driven rotor within the distributor. In another embodiment of the invention the distributor distributes water to at least one of a plurality of nozzles and draws water through at least one of the same plurality of nozzles. Other ones of the plurality of nozzles are neither outputting nor drawing in water. The function of a particular nozzle is dependent on the position of a rotor within the distributor. The rotor is motor driven whereby the function of a particular nozzle changes as a function of time as the rotor rotates. Each distributor of the invention is particularly adaptable for coupling to a fluid filled tank to provide time varying currents and eddies. The distributors thus provide a varying flow of water to a tank to disperse pollutants and contaminants and provide oxygen to the water.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: August 6, 1996
    Inventor: Joseph E. Foster
  • Patent number: 5530477
    Abstract: In a method and apparatus for decompressing with a video decompressor a compressed digital video signal representative of an input sequence of digital video frames, the processing power associated with the video decompressor is determined, and a decompression threshold value is selected from a plurality of candidate decompression threshold values in accordance with the processing power associated with the video decompressor. The video decompressor generates a decompressed digital video output signal in response to the compressed digital video signal, and the decompressed digital video output signal is monitored to determine whether the video decompressor is timely generating an output sequence of decompressed digital video frames. Compressed digital video frames are omitted from the compressed digital video signal provided to the video decompressor in response to the monitoring and in accordance with the decompression threshold.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: June 25, 1996
    Assignee: Intel Corporation
    Inventor: Rohan Coelho
  • Patent number: 5519439
    Abstract: A local subsampled color video signal is converted directly to a CLUT 8 format for local display as a preview image without being locally compressed and decompressed, while the same signal to be transmitted to a remote locate is compressed. The local preview display is thus generated using relatively little computer time and hardware, while still being of adequate quality for preview purposes.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: May 21, 1996
    Assignee: Intel Corporation
    Inventor: Michael Keith
  • Patent number: 5510740
    Abstract: A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: April 23, 1996
    Assignee: Intel Corporation
    Inventors: Robert Farrell, Sharad Mehrotra
  • Patent number: D368165
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: March 26, 1996
    Inventor: Joseph E. Foster