Patents Represented by Attorney, Agent or Law Firm Jon A. Gibbons
  • Patent number: 6745022
    Abstract: A distributor of prepaid wireless services provides a prepaid card representing an amount of prepaid wireless service that may be applied to any of a plurality of wireless service providers. Prepaid cards applicable to any of several wireless service providers are sold at retail points of sale and activated at the time of purchase. The card is then registered with a universal host where the card owner enters the card account number, PIN and the wireless device telephone number for which the prepaid service is to be applied. The universal host automatically selects one of the plurality of service providers in response to the phone number. The purchased prepaid service is then enabled for the wireless device corresponding to the phone number.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: June 1, 2004
    Assignee: DataWave Systems, Inc.
    Inventor: David Knox
  • Patent number: 6744080
    Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: June 1, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Alain Chantre, Helene Baudry, Didier Dutartre
  • Patent number: 6741472
    Abstract: A system for pivotally coupling two elements of a portable computer is disclosed. The system includes a hinge pin for pivotally coupling the two elements. The hinge pin includes a rod having a main axis and a first outer diameter. The hinge pin further includes a bore in a proximal portion of the rod having a first inner diameter, wherein the bore is aligned along the main axis. The hinge pin further includes a distal portion of the bore having a second inner diameter larger than the first inner diameter. The hinge pin further includes a groove stop within the bore, providing a surface for pulling the hinge pin along the main axis in a proximal direction. The system further includes a tool for extracting the hinge pin from the two elements, allowing the hinge pin to be pulled along the main axis in a proximal direction.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: May 25, 2004
    Assignee: WalkAbout Computers, Inc.
    Inventors: Hans A. Barth, Paul A. Wynn
  • Patent number: 6742177
    Abstract: A method to debug application interface calls made to a tamper-resistant software module. The method comprises the steps of: loading a first application to be debugged using a debugging application, wherein the application makes one or more function calls to a tamper-resistant software module. A debugger application for symbolically debugging the first application is run and the debugger application with an initialization file that performs the steps of: loading a client application running a client socket service; loading a server application running a server socket service; loading the tamper-resistant software module with one or more function calls made thereto by the first application. The client application translates the one or more function calls made to the tamper-resistant software module during the running of the debugger application into socket calls and returns any status received from the socket calls to the first application.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: May 25, 2004
    Assignee: International Business Machines Corporation
    Inventors: John J. Dorak, Jr., Stephen B. Cagle, Richard L. Spagna
  • Patent number: 6737886
    Abstract: An output buffer for causing a voltage (Vout) of an integrated circuit output line (OUT,OUT_PAD) to switch from a voltage of a first voltage line (VDD) to a voltage of a second voltage line (GND) and vice versa, comprises a current path switch circuit (111a,111b) activatable for causing a prescribed current (Is) to constantly flow between the first and second voltage lines during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated (Ic1) to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by the first and second voltage lines is thus kept substantially constant in the output line switching. In this way, the time derivative of the current flowing between the first and the second voltage lines is kept small and low switching noise is induced.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 18, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giacomo Curatolo, Ignazio Martines, Davide Torrisi
  • Patent number: 6735556
    Abstract: A method, computer readable medium and a structure for real-time simulation, which allows the user to manipulate model parameters and see the simulated result in real-time as the model is changed. The simulated result is visually compared with the data, allowing the user to refine the model. In one embodiment, the invention is used for evaluating medium energy ion scattering (MEIS) data, as well as conventional Rutherford backscattering data. It is important to realize that the invention is not limited to ion beam analysis, or to scientific data analysis. The invention can be used for evaluating any type of complex system where a well-defined simulation procedure exists. The model evaluation must proceed quickly enough to provide a real-time, visual display for the user.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventor: Matthew W. Copel
  • Patent number: 6735200
    Abstract: A method and apparatus for managing communications in a distributed computing system wherein a plurality of computers are interconnected with a communications network. At least a portion of the network is established as a subnetwork with at least one node attached to the subnetwork. The node in the subnetwork multicast a verification message over the subnetwork in which it is attached. A subnetwork leader for each subnetwork is identified and gathers the verification message sent from each node in the subnetwork. The subnetwork leader assembles each verification received into a subnetwork list. The subnetwork list is sent a node identified as the network leader. The network leader assembles each subnetwork list received into a master list and sends this master list out to the subnetwork leaders. In turn, the subnetwork leaders for each subnetwork multicast the master list out to each node. In one embodiment, the communications between each subnetwork leader and the network leader is over multicast.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventor: Marcos N. Novaes
  • Patent number: 6732189
    Abstract: A method for maintaining the reachability of IP multicast communications across a communications network with one or more subnetworks wherein each subnetwork comprises at least one node coupled thereto and a node identified as a subnetwork leader and the communications network comprises one node identified as a network leader. The method comprising the steps of: receiving a host address list containing a list of all the network addresses of the, nodes in a network including at least two subnetworks, and a node in each subnetwork identified as a subnetwork leader; using the host address list for determining which subnetworks the subnetwork leaders are associated therewith. The reachability of at least one subnetwork leader in the network is periodically monitored.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: May 4, 2004
    Assignee: International Business Machines Corporation
    Inventor: Marcos N. Novaes
  • Patent number: 6731557
    Abstract: A method (1110a;1110b) of refreshing an electrically erasable and programmable non-volatile memory (100) having a plurality of memory cells (Mhk) is proposed. The method includes the steps of: verifying (1106-1114; 1152-1162) whether a memory cell has drifted from a correct condition (i.e., a predetermined voltage and/or voltage range), and individually restoring (1116-1130) the correct condition of the memory cell if the result of the verification is positive.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 4, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventor: Franco Enrico Beretta
  • Patent number: 6728135
    Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: April 27, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Cyrille Dray, Daniel Caspar, Richard Fournel
  • Patent number: 6718324
    Abstract: A system and method of metadata search ranking is disclosed. The present invention utilizes a combination of popularity and/or relevancy to determine a search ranking for a given search result association. Given the exponential growth rate currently being experienced in the Internet community, the present invention provides one of the few methods by which searches of this vast distributed database can produce useful results ranked and sorted by usefulness to the searching web surfer. The present invention permits embodiments incorporating a Ranking System/Method (0100) further comprising a Session Manager (0101), Query Manager (0102), Popularity Sorter (0103), and Association (0104) functions. These components may be augmented in some preferred embodiments via the use of a Query Entry means (0155), Search Engine (0156); Data Repository (0157), Query Database (0158), and/or a Resource List (0159).
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Stefan B. Edlund, Michael L. Emens, Reiner Kraft, Jussi Myllymaki, Shanghua Teng
  • Patent number: 6711466
    Abstract: A system and method for maintaining a dispensing system a desired distance between a dispenser and a surface is shown. The system includes a light-emitting device, connected to the dispenser, that emits light in the direction of the surface. The emitted light is reflected off of the surface as well as a mirror connected to the dispenser. Subsequently, all reflected light is received by a sensor. Using the sensor data, a computer calculates the distance between the dispenser and the surface. A servo device then adjusts the location of the dispenser, in accordance with the calculated distance, in order to maintain the desired distance between the dispenser and the surface. One advantage of the system and method is the increased ability to maintain a desired distance between the dispenser and the surface. This can lead to increased and higher quality production by a dispensing system.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Richard A. John, Robert J. von Gutfeld
  • Patent number: 6708203
    Abstract: A method is illustrated in the flow diagram 100 of FIG. 1. A processor 1001 renders a message 1025 for the processor operator's education during times of processor latency 1015, such as dialing onto any network, such as the Internet. This wait time 1017 is normally non-productive, and therefore can be used in such a way as to be non-invasive. It is also understood that this time is short, so as to make other actions, such as getting up from the desk, not attractive. Finally, even if the wait time was, or became, very short, the present invention provides the first message 1025 to the process operator that has been filtered. This filtering is a balance of the message owner's willingness to out bid other messages, the time of the day, the location of the operator, and finally the operator's likes and dislikes.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: March 16, 2004
    Assignee: The DelFin Project, Inc.
    Inventors: Michael G. Makar, Joseph M. Mosley, Tracy A. Tindall
  • Patent number: 6708308
    Abstract: This invention is a Viterbi algorithm combined with the use of error filters outputs to produce bit reliabilities. The present invention is a SOVA-like method using error filters to reduce the complexity of bit reliability determination further than that of the ordinary SOVA method. Error patterns corresponding to each of a handful of dominant i.e., most common error patterns are determined from experimental data. Error filters determine likelihoods of each postulated error pattern. These likelihoods are then combined to produce bit reliabilities that may be passed on to an outer error correction decoder. The filters, typically six or seven of them, resolve most of the errors thereby simplifying computation dramatically.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jorge Campello De Souza, Brian H. Marcus, Richard M. H. New, Bruce A. Wilson
  • Patent number: 6702439
    Abstract: An eyeglass frame assembly for coupling clip-on auxiliary spectacles to primary spectacles. The primary spectacles having a pair of cavities formed on the inside surface of rear extensions and the clip-on spectacles having a pair of pins mounted to the outside surface of a pair of hinged extensions, wherein the pins are capable of positively engaging the cavities by exerting outward forces. The hinged extensions allow the clip-on spectacles to swing up and to place the auxiliary lenses mounted within the clip-on spectacles to be outside the vision path of the user.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: March 9, 2004
    Inventor: Jung I. Lee
  • Patent number: 6691104
    Abstract: A system and method for associating a personalized application tool and/or service in response to data supplied by any number of search requests is disclosed. The present invention in some preferred embodiments integrates a Session Manager (0601), Registration Manager (0602), Result Analyzer (0603) Tool/Service Integrator (0604), Request Server (0605) in conjunction with a User Registration Profile Database (0606) and a DTD Search Engine Schema (0607). Several preferred embodiments of the present invention are configured to process user search requests (0611) comprising Internet search queries (0612) that are subsequently processed by an Internet Search Engine (0613) under control of a Session Manger (0601). The focus of the present invention is to automate the post-processing of search results by automatically applying a user-specified data analysis tool to the search results, thus improving the overall efficiency of the searching and data analysis functions by a given user.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: February 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Reiner Kraft, Neelakantan Sundaresan
  • Patent number: 6688827
    Abstract: A protective device for an aciculate object includes a body, a capture, and a protective cap. The body is a geometric shape with two ends. The body has a longest side of length L1. The body is resistant to deformation along an axis parallel to the longest side of the body. The capture is formed into the body at one end. The protective device is pushed over a pointy or pointed end of the aciculate object positively engaging the capture of the protective device. The capture retains the aciculate object and resists movement of the aciculate object coaxially off the aciculate object and in a direction normal to an axis parallel to the longest side of the body. The protective cap is mounted to the end of the body opposite the capture. The protective cap has a diameter L2, such that L2 is less than L1. The protective cap is resistant to penetration from the pointy or pointed of the aciculate object.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: February 10, 2004
    Inventor: Ronald Gelb
  • Patent number: 6689655
    Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: February 10, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Francois Leverd, Paul Ferreira
  • Patent number: 6677206
    Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: January 13, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Patelmo, Federico Pio
  • Patent number: 6673703
    Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: January 6, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Olivier Menut, Herve Jaouen