Patents Represented by Attorney, Agent or Law Firm Jon W. Hallman
  • Device and method with generic logic blocks
    Patent number: 6765408
    Abstract: A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: July 20, 2004
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jason Cheng, Cyrus Tsui, Satwant Singh, Albert Chen, Ju Shen, Clement Lee
  • Direct downconversion receiver
    Patent number: 6745020
    Abstract: A direct downconversion receiver combines a received RF signal and a local oscillator (LO) signal to form a combined signal. The local oscillator signal is also phase-shifted by approximately 90 degrees to form a quadrature signal. A mixer forms the product of the combined signal and the quadrature signal to produce a baseband output signal.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: June 1, 2004
    Inventors: Eugene Rzyski, Todd Wangsness
  • Soft snap-down optical element using kinematic supports
    Patent number: 6738177
    Abstract: The snapped-down position of an optical element is defined by its contact with a plurality of kinematic supports on an associated platform, or on electrodes placed on that platform. Compliant flexures may be provided in association with one or more kinematic supports, such that fine adjustments of the optical element can be made by deflecting the optical element to cause compression of one or more flexures.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: May 18, 2004
    Assignee: Siwave, Inc.
    Inventors: Roman C. Gutierrez, Tony K. Tang, Cathleen Jones, Robert J. Calvet
  • Automatic configuration of delay parameters in a dynamic memory controller
    Patent number: 6370067
    Abstract: A memory controller configured according to a delay pair for communicating with a memory device automatically selects optimal delay pairs by testing whether successful communication exists at various values for the delay pairs. The resulting set of delay pairs allowing successful communication are divided into a boundary set and non-boundary set. An optimal delay pair from the non-boundary set is chosen according to its relationship to delay pairs in the boundary set.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: April 9, 2002
    Assignee: Ishoni Networks, Inc.
    Inventors: Ka-pui Ko, Isaac H. Wong, Keith V. Ngo, Jau-Wen Ren, Jiinyuan Lee
  • System and method for concurrent buffer insertion and placement of logic gates
    Patent number: 6367051
    Abstract: A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 2, 2002
    Assignee: Monterey Design Systems, Inc.
    Inventors: Lawrence Pileggi, Sharad Malik, Emre Tuncer, Abhijeet Chakraborty, Satyamurthy Pullela, Altan Odabasioglu, Douglas B. Boyle