Patents Represented by Attorney, Agent or Law Firm Jonathan A. Small
  • Patent number: 7973311
    Abstract: A photosensor structure includes a pixel metal layer disposed in physical and electrical contact with a pixel thin film transistor and a lower sensor layer of a p-i-n photosensor. The pixel metal layer extends laterally to an extent less that the lower sensor layer such that an overhang region is defined below the lower sensor layer and the adjacent the lateral edge of the pixel metal layer. When the relatively thick intrinsic sensor layer is formed over the lower sensor layer, it attaches to the upper surface and, due to the presence of the overhang region, the lateral edge of the lower sensor layer, forming a discrete intrinsic sensor layer structure over the pixel which is physically isolated from adjacent corresponding structures. This isolation allows for thermal expansion and contraction during formation of the intrinsic sensor layer without cracking the intrinsic sensor layer structure.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 5, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Rene Lujan, William S. Wong
  • Patent number: 7955783
    Abstract: A method for masking regions of photoresist in the manufacture of a soldermask for printed circuit boards is disclosed. Following application of photoresist over patterned traces on a substrate, a sheet-like thin film is applied over the photosensitive material. The thin film may adhere to the photosensitive material by way of the adhesive state of the photosensitive material or by way of an adhesive applied to the photosensitive material or the thin film or carried by the thin film. Digital mask printing may proceed on the surface of the thin film. The photosensitive material may then be exposed through the printed photomask, the thin film (with photomask) removed, and the photosensitive material developed.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 7, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eric Shrader, Uma Srinivasan, Clark Crawford, Scott Limb
  • Patent number: 7927905
    Abstract: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 19, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene Michael Chow, Pengfei Qi
  • Patent number: 7889416
    Abstract: Scan line position error resulting in banding, bow, skew, etc. is corrected by way of an agile beam steering mirror assembly in a ROS printing system and the like. The agile beam steering mirror system comprises a piezoelectric bending actuator fixedly mounted to a substrate at a proximate end thereof. A mirror structure is mounted at a free distal end of the bending actuator. Voltage applied to the bending actuator causes rotation of the mirror to thereby correct for positional errors of the scan line. Correction waveforms may be stored in control memory associated with the agile beam steering mirror assembly. A capacitive sensing circuit using a sensing electrode located beneath the free end of the bending actuator may be used in a feedback arrangement to determine and control mirror position.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: February 15, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Timothy D. Stowe
  • Patent number: 7884361
    Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 8, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: William Wong, Rene Lujan, Eugene Chow
  • Patent number: 7855098
    Abstract: A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: December 21, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Peter Kiesel, Oliver Schmidt
  • Patent number: 7856040
    Abstract: The AlGaN upper cladding layer of a nitride laser diode is replaced by a non-epitaxial layer, such as metallic silver. If chosen to have a relatively low refractive index value, the mode loss from absorption in the non-epitaxial cladding layer is acceptably small. If also chosen to have a relatively high work-function, the non-epitaxial layer forms an electrical contact to the nitride semiconductors. An indium-tin-oxide layer may also be employed with the non-epitaxial cladding layer.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: December 21, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: David P. Bour, Christopher L. Chua, Noble M. Johnson, Zhihong Yang
  • Patent number: 7842521
    Abstract: The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: November 30, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Scott J. Limb
  • Patent number: 7843982
    Abstract: A method of avoiding device failure caused by facet heating is described. The method is particularly applicable to a semiconductor laser. In the method, a semiconductor laser facet including GaAsN is hydrogenated such that the bandgap within the facet is greater than the bandgap in the active region of the InGaAsN laser. The increased bandgap reduces absorption of light in the facet and the associated heating that results.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 30, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Michael A. Kneissl, Noble M. Johnson, Peter Kiesel
  • Patent number: 7838330
    Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: November 23, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Peter Kiesel, Oliver Schmidt
  • Patent number: 7809211
    Abstract: Image normalization examines the pixels of two frames, most commonly sequentially obtained sub-images, and mathematically determines the displacement of those pixels from the first frame to the second based on pixel data. The pixel data is obtained from a scanning device, and may be for example grayscale value. The image may be for example that of a user's fingerprint, and the image normalization used to form a computed image of the fingerprint from a plurality of sub-images obtained from a fingerprint scanner. The computed image may be stored, compared to a reference frame or otherwise processed, for example for identifying the user.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: October 5, 2010
    Assignee: Upek, Inc.
    Inventors: Peter Taraba, Giovanni Corradini, Martin Subert
  • Patent number: 7804090
    Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: September 28, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: William Wong, Rene Lujan, Eugene Chow
  • Patent number: 7783587
    Abstract: An apparatus for storage, selective inspection, and execution of complex, contingent rules, comprises a computer having one or more central processing units, a user interface, and magnetic, optical, or other media for data and program storage and retrieval. Rules are defined partly as programs and partly as data. Access procedures are provided for selecting certain appropriate rules under defined conditions. Output procedures are provided for conveying the results of the rule selections to people, to the computer executing the rules, and to other computers.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: August 24, 2010
    Inventors: Jeffrey G. Long, Jimmy J. Jenkins
  • Patent number: 7768273
    Abstract: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes a first capacitor plate placed vertically under the upper surface of a dielectric layer and a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate. Electrostatic discharge protection relative to electrostatic potential that may be carried by an ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 3, 2010
    Assignee: UPEK, Inc.
    Inventors: Alexander Kalnitsky, Alan Kramer
  • Patent number: 7764721
    Abstract: A method and structure for adjusting the wavelength output of a semiconductor device is described. In the method, the hydrogen concentration in an active region of the semiconductor device is adjusted either during fabrication or after the device has been fabricated. The adjustment provides a simple technique for fine tuning many device types including regular lasers and VCSEL structures. The adjustment also allows for mass production of lasers of many different frequencies on a single wafer substrate, a system particularly desirable for wavelength division multiplexing systems.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: July 27, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Michael A. Kneissl, Noble M. Johnson, Peter Kiesel
  • Patent number: 7749916
    Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: July 6, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: William Wong, Scott Limb, Michael Chabinyc, Beverly Russo, Rene Lujan
  • Patent number: 7751455
    Abstract: A novel indium gallium nitride laser diode is described. The laser uses indium in either the waveguide layers and/or the cladding layers. It has been found that InGaN waveguide or cladding layers enhance optical confinement with very small losses. Furthermore, the use of InGaN waveguide or cladding layers can improve the structural integrity of active region epilayers because of reduced lattice mismatch between waveguide layers and the active region.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 6, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Michael A. Kneissl
  • Patent number: 7741147
    Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 22, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Peter Kiesel, Oliver Schmidt
  • Patent number: 7718455
    Abstract: A method of forming a buried aperture in a nitride light emitting device is described. The method involves forming an aperture layer, typically an amorphous or polycrystalline material over an active layer that includes a nitride material. The aperture layer material typically also includes nitride. The aperture layer is etched to create an aperture which is then filled with a conducting material by epitaxial regrowth. The amorphous layer is crystallized forming an electrically resistive material during or before regrowth. The conducting aperture in the electrically resistive material is well suited for directing current into a light emitting region of the active layer.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: May 18, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Zhihong Yang
  • Patent number: 7648860
    Abstract: A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: January 19, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Rene Lujan, William S. Wong